Cadence CONFRML 23.20.200 for linux
As designs continue to get more complicated in order to meet aggressive requirements for power, performance, area, and time to market, the formal verification of the designs continues to be a staple and must-have signoff metric to ensure silicon success.

 

 

Cadence^® Conformal^® technologies provide you with an independent equivalence checking solution enabling verification of designs from RTL to final netlists from P&R.

 

In addition to standard equivalence checking, the Conformal solution offers:

Static verification solutions for low-power designs, including low power-aware equivalency checking

Automated ECO generation capabilities for minimal netlist changes and faster tapeouts

Constraint designer for clock domain crossing and SDC verification solutions