AI-Driven Automated Approach to Chip Design—Delivering Improved PPA and Productivity

Engineering teams are overloaded and need help to keep up with the ever-increasing demands on chip designs. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, artificial intelligence (AI)-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus will intelligently optimize the design to meet these power, performance, and area (PPA) goals in a completely automated way.

By adopting Cadence Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cadence Cerebrus full-flow reinforcement learning technology and large language model (LLM) capabilities in Cadence.AI Generative AI Platform, engineering team productivity is greatly improved.