Cadence XCELIUM Main 25.09.003: High-Performance Functional Verification Platform

XCELIUM Main 25.09.003 is the latest release of Cadence's high-performance simulation and functional verification platform for complex SoC designs. It delivers multi-core simulation acceleration, advanced debug capabilities, and power-aware verification for digital, analog, and mixed-signal designs .

Key Features

XCELIUM Main Simulator

• Multi-Core Simulation: Advanced parallel simulation engine with up to 10x faster simulation performance for large-scale SoCs

• ML-Based Debug: AI-powered root-cause analysis to reduce debug time

• Multi-Language Support: VHDL, Verilog, SystemVerilog, e, SystemC, C/C++, UVM

• Power-Aware Simulation: UPF-based low-power verification with dynamic power switching

XCELIUM Enterprise Simulation

• Enterprise-Level Capacity: Supports designs exceeding 10 billion gates; scalable across thousands of simulation cores

• Accelerated VIP: Native support for industry-standard protocols (PCIe, CXL, USB, Ethernet, MIPI, DDR)

• Emulation-Ready: Seamless integration with Palladium emulation platform

Additional Capabilities

• Memory Modeling: In-system memory modeling for real-world traffic generation

• Safety & Reliability: ISO 26262 automotive safety simulation (ASIL D certified)

• Cloud-Ready: Native support for hybrid cloud simulation deployment