Cadence® Encounter® Digital Implementation (EDI) System provides the most effective methodology to maximize performance, and minimize area and power for high-performance, 100M+ instance and power-efficient designs. Integration with the Virtuoso® custom design environment ensures seamless data transfer and increases productivity for mixed-signal designs. EDI System also supports advanced 20/22nm and 14/16nm FinFET process technologies and system-in-package/3D-IC design. With these capabilities, EDI System delivers the most comprehensive and deterministic solution for physical implementation of today’s most demanding SoCs. Benefits Predictability and convergence Provides full-chip implementation in a single environment Enables design exploration, fast and accurate chip feasibility analysis, including automated floorplan synthesis and ranking, as well as hierarchical budgeting and planning for convergent hierarchical implementation results GigaOpt throughout the flow and natively integrated CCOpt technologies deliver better power, performance, and area results for high-performance designs, allowing block implementation to meet and exceed aggressive goals Route-driven optimization, new track assignment, and signoff optimization produce deterministic results and accelerate design closure Productivity and faster time to market Supports hierarchical methodologies including bottom-up block-based flows, top-down black-box flows, and hybrid flows with partitioning and time budgeting Key technology adapts to growing capacity requirements while still retaining the relevant timing, placement, and congestion information to accurately plan and implement 100+M instance designs FlexModels provide up to 90% netlist compression and an optimized interface for accurate design exploration and planning, resulting in faster turnaround time and one-pass implementation handoff Performance scalability Delivers industry-leading performance and capacity for 100+M instance, complex chips Offers a complete, end-to-end, multi-core parallel processing backplane and infrastructure Provides best-in-class, efficient multi-corner functionality to significantly improve turnaround time Differentiated product development with lower production costs Includes comprehensive support for 22/20nm and 16/14nm FinFET designs to handle design scale and complexity as well as new DFM requirements Supports signoff correlated double-patterning physical implementation, from placement and routing to timing, power, and physical signoff Enables concurrent chip/package co-design and optimization with integrated capabilities such as automatic area and peripheral I/O placement and flip-chip RDL routing