Cadence Xcelium v23.03.004_Xcelium Logic Simulator

Description

Cadence Xcelium v23.03.004

Fastest Simulator to Achieve Verification Closure for IP and SoC Designs

Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.

Broad Language Support

Support for SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards

 
Best-in-Class Performance

Automated parallel and incremental build technologies to support the compilation of big SoC designs and best-in-class simulation engines for best regression throughput, including a multi-core engine to speed-up long-running test cases

 
Accelerate with Apps

Xcelium Apps such as mixed-signal, machine learning-based test compression, and functional safety for ease of mixing and matching different technologies needed throughout the design and verification cycles

Portfolio of Apps

Xcelium Apps work natively with the Xcelium Logic Simulator and enable design teams to achieve the highest verification performance at both the IP and full-chip level of modern SoC designs.

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