cadence MVS 14.21


Magillem Verification Scenarii New Magillem Verification Scenarii (MVS) Environment Configures Validation of IP & Sub-systems, and Automates Test Bench Generation Supports ARM cores integration and verification Single access mechanism to all resources of the design database for concurrent validation strategies Functional validation of large SOCs by multiple teams is significantly improved with IP XACT (IEEE1685) standard Paris, 25 October 2011,- MVS, Magillem Verification Scenarii, is the latest software proudly launched by Magillem , the leader of IP XACT based solutions for improved flow methodology : Complex SoCs require three layers of partitioning: functional sub systems with configurable parameters for architects, logical blocks (hierarchical assembly for implementation) used by designers and integrators, and functional validation subsets necessary for verification teams. MVS is dedicated to those validation teams. Once IP and VIP blocks have been packaged in IP XACT, the SoC has been assembled with Magillem Platform Assembly(MPA), the registers have been captured with Magillem Register View (MRV), the sequences have been written by firmware engineers thanks to Magillem Sequence Editor(MSE), test teams need an environment to configure IP and sub systems they want to validate, and to automate the generation of the test bench : system clocks, hardware sequences, monitor and probes insertion, file set for compilation and simulation…this environment is provided by MVS and its generators. MVS offers a GUI mode and a CLI mode. The graphical mode makes it easy for the engineer to select and configure their test bench MVS offers a Sequence Editor based on MSE to write functional sequences matching specification configuration and to run the tests on registers. If MRV has been used to capture registers, it is also possible to generate register connectivity tests, in order to verify registers access as defined in the specification. MVS is leveraging the IP XACT XML metadata, as it allows to access all facets of each IP, each facet can show a different language at multiple abstraction levels, VHDL, Verilog, System C, e language, System Verilog, as defined for each step of the flow. Without IP XACT, managing the IP database is much more complicated, and requires regenerating the test bench before compiling for each simulation tool. Thanks to the use of IP XACT, MVS provides a single API to handle all the resources of an IP or a platform at once. Time savings are invaluable! Various validation strategies can be implemented without duplicating efforts (OVM, UVM...). For example, a sub system can be tested for one set of parameters with Cadence Incisive Enterprise Simulator ™ while the top level will be running on Mentor Questa™. “MVS is a no-learning-curve add-on for all our customers already familiar with the Magillem software suite, now the one-stop-shopping front end environment for IP reuse based design strategies. Verification engineers will enhance and change their flow very easily to adapt it to new challenges posed by very large SOCs” says Cyril Spasevski, CTO and co founder of MAGILLEM.”MVS has been extensively tested by two of our largest customers among the top 6 in the semiconductor industry, both designing an ARM based complex SOC, and they are raving about their improved performance , quality of verification and time efficiency.”


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