Cadence SPB 16.2 Linux

Description

Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers. I will be talking about the improvements in this release over a few blog posts in coming days and weeks. First and foremost, we have added a Constraint Driven PCB Design Flow for build-up designs to accelerate miniaturization. As you know, customers in high-end consumer electronics market place, mobile phone makers, GPS navigation system makers have been dealing with miniaturization for quite some time now and have been using build-up process to fabricate PCBs. With smaller and smaller pin pitch BGAs being introduced -- with 0.8 mm pin pitch or lower at 0.65, 0.5, 0.4 mm pin pitches -- there is no way to drill a through hole via through the BGAs. While miniaturization is not necessarily the primary objective for customers in many other market segments (such as computing, networking), they are being forced to use build-up technology for fanning out a BGA -- particularly if the BGA has 3 or 4 rows of pins on each side. For cost reasons most customers tend to use 2 build-up layers on each side of the PCB and have the traditional rigid PCB as the core. For customers in most, if not all, market segments having a Constraint Driven PCB design flow is a requirement. I have heard over the past 8-10 years about the number of nets that have high-speed is growing. With the migration to standards based interfaces the number of constraints on nets is also increasing. Particularly with DDRx standard there is not only an increase in the number of constraints on nets but there are a lot of additional constraints that are interdependent on each other. For example, for DDR2 memories all data signals in a byte lane must be matched in length and delay. Clocks must be longer than the lengths of Address, Command and Control signals at the same time length of all the clock signals must be between the longest Data Strobe signal and the shortest Data Strobe Signal. When customers who are designing with DDRx are forced to move to build-up technology for BGA fanouts, they require a system that can handle both the design requirements coming from such standards based interfaces and also from the build-up technology using HDI. Many Cadence Allegro PCB users have been doing blind and buried vias for a while now with the Constraint Driven Flow. They have been asking us to enhance the capabilities to make it easier to design PCBs with HDI. We really focused on this area to ensure that our customers continue to get the benefit of our proven Constraint Driven PCB design flow while working on HDI designs. It's not enough to do just HDI without a robust and comprehensive Constraint driven PCB design as a backbone. Without the CD flow, customers may be able to create HDI designs faster only to find out later in the design cycle to find out that the high-speed interfaces don't work. I want to hear your thoughts and comments about this topic. Please share below. I would also like to invite some of the customers who worked closely with us to comment on the content in SPB 16.2, particularly on Constraint Driven HDI PCB Design Flow.

Download-

  • Previous:Cadence IFV 8.1 Linux
  • Next:Cadence SoC Encounter 8.1 Linux
  • Letters A B C D E F G H I J K L M N O P Q R S T U V W X Y Z TOP