Cadence  Incisive  Formal Verifier(IFV) allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and detecting the corner-case errors that other methods often miss. Incisive Formal Verifier integrates easily into established design and assertion-based verification flows through its support of industry-standard languages.

Features/Benefits

• Speeds time to block design closure with early error detection, analysis, and debug
• Reduces risk of re-spin by finding bugs that other verification approaches miss
• Eases chip-level verification by delivering higher block-level verification quality
• Leverages the same assertions as Incisive simulation, acceleration, and emulation technologies
• Supports all industry-standard assertion formats, including SystemVerilog Assertions (SVA), Property Specification Language (PSL), the Open Verification Library (OVL), and the Incisive Assertion Library