ModelSim SE - High Performance Simulation and Debug
ModelSim SE is our UNIX, Linux, and Windows-based simulation and debug environment, combining high performance with the most powerful and intuitive GUI in the industry.
What's New in ModelSim SE?
- Improved FSM debug options including control of.....
Language : english Authorization: Business Freshtime：2010-08-24 Size: 245 MB
Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre's i.....
Language : english Authorization: Pre Release Freshtime：2010-08-18 Size: 1.3 GB
National Instruments has been a leader in machine vision and image processing for nearly a decade and currently supports thousands of different cameras. To acquire, display, save, and monitor images from cameras, use NI Vision Acquisition software, which is included with all NI frame grabbers and s.....
Language : english Authorization: Pre Release Freshtime：2010-08-13 Size: 1.2 GB
NI LabVIEW 2010 software features an improved back-end compiler that generates optimized machine code, increasing your application's run-time execution up to 20 percent. Additionally, LabVIEW 2010 tackles top support issues with streamlined software installation, Web-based hardware configuration, a.....
Language : english Authorization: Pre Release Freshtime：2010-08-13 Size: 847 MB
Keil combines the ARM RealView Compiler with the uVision Integrated
Development Environment, providing developers with a feature-rich
environment optimized for ARM-powered microcontrollers.
Keil development tools for ARM7, ARM9, and Cortex-M3 microcontrollers
are easy to learn and use, ye.....
Language : english Authorization: Pre Release Freshtime：2010-08-11 Size: 189 MB
What's New in the ISE Design Suite 12.2 for Logic Designers
Project Navigator
* SmartXplorer:
o Consistent use of TRCE options between Project Navigator and SmartXplorer.
o Ability to perform Power Analysis with SmartXplorer runs.
o Additional resource utilization .....
Language : english Authorization: Pre Release Freshtime：2010-08-10 Size: 2.8 GB
Want a powerful, yet easy to use simulation environment?
SynaptiCAD's simulation and debugging tools provide a
standard interface for controlling all of your simulation
tools. SynaptiCAD's timing diagram editors have the most
extensive and accurate timing anal.....
Language : english Authorization: Pre Release Freshtime：2010-08-10 Size: 126 MB
Version 10.0 supports Altera's new high-performance, built-for-bandwidth
devices: Stratixr V GX and GS FPGAs with integrated 12.5-Gbps
transceivers. Stratix V GX FPGAs are optimized for high-performance,
high-bandwidth applications. Stratix V GS FPGAs target high-performance,
variable-preci.....
Language : english Authorization: Business Freshtime：2010-08-09 Size: 4 GB
IAR visualSTATE is a set of highly sophisticated and easy-to-use development tools for designing, testing and implementing embedded applications based on state machines.
IAR visualSTATE
Click image to enlarge
It provides advanced verification and validation utilities and generates very compact C.....
Language : english Authorization: Pre Release Freshtime：2010-08-09 Size: 75 MB
Design Reuse
A mechanism through which a block of items in a design may be stored and reused in one or more designs.
Second Component Name
You can now add two PCB component names so they can exist in different locations on different layers e.g. Silkscreen and Assembly layers
New Attribute Editor.....
Language : english Authorization: Pre Release Freshtime：2010-08-09 Size: 185 MB
What's New in S-Edit v15.01
Spice and Verilog-A Text Views
S-Edit now supports Spice and Verilog-A text views. Any combination of i) schematic,
ii) Spice, and iii) Verilog-A view may be saved for a cell. The view that is used when
simulating is given by a priority list of view types and view names d.....
Language : english Authorization: Pre Release Freshtime：2010-07-31 Size: 678 MB
Ansoft Designer® is an integrated schematic and design management front-end for Ansoft's best-in-class simulation technologies, HFSS™, Q3D Extractor®, and SIwave™. Ansoft Designer is the foundation for a highly accurate design flow that allows users to precisely model and simulate complex analog.....
Language : english Authorization: Pre Release Freshtime：2010-07-31 Size: 670 MB
The AWR Design EnvironmentTM (AWRDE) 2010 version includes the following new features, enhancements, and user interface changes.
AWRDE documentation includes both PDF documents and CHM (Help) files. The PDF files are available for download from the AWR website and are also included on AWRDE CDs. Th.....
Language : english Authorization: Pre Release Freshtime：2010-07-31 Size: 465 MB
LP Wizard Suite is a complete set of tools to build and manage your CAD library and documentation using proven technology from IPC. LP Suite is the only CAD library generation tool that is officially approved by IPC to match the IPC-7351 standard. A full featured 30-day evaluation version is availab.....
Language : english Authorization: Pre Release Freshtime：2010-07-31 Size: 312 MB
VCS®, with multicore technology, delivers a 2x verification speed-up that helps users find design bugs early in the product development cycle. VCS multicore technology cuts down verification time by running the design, testbench, assertions, coverage and debug in parallel on machines with multiple .....
Language : english Authorization: Pre Release Freshtime：2010-07-30 Size: 354 MB
Saber is a multi-domain modeling and simulation environment that enables full-system virtual prototyping for applications in analog/power electronics, electric power generation/conversion/distribution and mechatronics. Decades of industry success and innovation have earned Saber a reputation as the .....
Language : english Authorization: Pre Release Freshtime：2010-07-29 Size: 1.2 GB
MPro 2010.07 is a maintenance release for EMPro 2010.
EMPro is a new design platform for analyzing the electromagnetic effects of RF and microwave components such as high-speed IC packages, antennas, on-chip and off-chip embedded passives and PCB interconnects. EMPro features the most modern design.....
Language : english Authorization: Pre Release Freshtime：2010-07-23 Size: 918 MB
VICTORY PROCESS
3D PROCESS SIMULATOR
VICTORY PROCESS is a general purpose 3D process simulator. VICTORY PROCESS includes a complete process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit. Proprietary mo.....
Language : english Authorization: Pre Release Freshtime：2010-07-21 Size:
High Level Synthesis
High Level Synthesis reduces the manual effort required to create and completely verify synthesizable RTL code. Design size and complexity continue to push traditional RTL design and verification methodologies to their limits.
Catapult C Synthesis
Full-Chip High-Level Synthesi.....
Language : english Authorization: Pre Release Freshtime：2010-07-21 Size: 215 MB
X-HDL 4 is the premier Verilog VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, "hand tweaks" of the translated code. X-HDL also contains specialized algorithms which are very effective in translating beha.....
Language : english Authorization: Pre Release Freshtime：2010-07-20 Size: 12 MB
HyperLynx® Signal Integrity enables engineers to quickly and accurately analyze and eliminate signal integrity and EMI/EMC design problems early in the design cycle. HyperLynx Signal Integrity comes ready to use in virtually any PCB design flow and offers unprecedented time-to-results, improving pr.....
Language : english Authorization: Pre Release Freshtime：2010-07-16 Size: 226 MB
Genesys 2010.05 was developed based on extensive inputs from a large Genesys user community. This release of Genesys went through the most thorough quality assurance (QA) and early access (EA) customer testing compared to all previous versions of Genesys.
Not only does this release address multiple.....
Language : english Authorization: Pre Release Freshtime：2010-07-13 Size: 551 MB
Vera language was orginally developed in Sun Micro Systems for internal ASIC verification projects. Later VERA language with VERA compiler was marketed by System Science. System Science later sold Vera to Synopsys. Synopsys released closed Vera language as openVera, which was later implemented in.....
Language : english Authorization: Pre Release Freshtime：2010-07-13 Size: 287 MB
Quartus® II software version 10.0, the industry's #1 software in performance and productivity for CPLD, FPGA, and HardCopy ASIC designs, is now available. Download Quartus II software today!
Version 10.0 supports Altera's new high-performance, built-for-bandwidth devices: Stratix® V GX and GS FPG.....
Language : english Authorization: Pre Release Freshtime：2010-07-10 Size: 4.3 GB