Mentor Graphics Tessent 2013

Description

Tessent combines features of deterministic scan testing, embedded pattern compression, built-in self test, specialized embedded memory test and repair, and boundary scan, as well as board and system-level test technologies. The Tessent product suite provides comprehensive silicon test and yield analysis solutions that address the challenges of manufacturing test, debug, and yield ramp for today’s SoCs. Built on the foundation of the best-in-class solutions for each test discipline, Tessent brings them together in a powerful test flow that ensures total chip coverage. Tessent® MemoryBIST provides a complete solution for at-speed testing, diagnosis, and repair of embedded memories. The solution’s architecture is hierarchical, allowing BIST and self-repair capabilities to be added to individual cores as well as at the top level. Tessent MemoryBIST includes a unique comprehensive automation flow that provides design rule checking, test planning, integration, and verification all at the RTL or gate level.. Features and Benefits Fast self-test and self-repair IP integration, as well as reuse of embedded memory test inserted cores, shorten time-to-market. Design-time algorithm programming allows for quality improvement and test time optimization. Field algorithm programming provides full control of quality and test time trade-offs. Built-in row- and column-based repair analysis reduces test time for repairable memories. Options Tessent MemoryBIST Repair Tessent MemoryBIST Field Programmable On-chip eFuse-based repair supports any third-party repairable SRAMs. Supports any number of power domains distributed across any number of physical blocks.

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