Cadence Design Systems, Inc. announce that hotfix version 003 for 16.60 release available. This update includes some critical bug fixes. Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation. This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology. 1077728 APD EXTRACT Extracta.exe generate the incorrect result 1084711 APD DXF_IF Padstacks with offsets cause violations in Export > DXF 1090369 SIG_INTEGRITY LICENSING Impedance value not updating in OrCAD PCB Designer 1093050 ALLEGRO_EDITOR DRC_CONSTR Taper trace on diff pairs not checking to min line spacing. 1093563 SPECCTRA ROUTE PCB Router crashes with reduce_padstack set to on 1093717 APD DATABASE Design is crashing in Tools > Update DRC and in Dbcheck but seems inconsistent 1094788 SIP_LAYOUT WIREBOND Wirebond edit move command 1095786 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro PCB crashes when running DBDoctor 1096234 ALLEGRO_EDITOR DFA Via pad connected to shape didnїt show up after їSuppress unconnected padsї option. 1096313 RF_PCB LIB_TRANSLATOR Allegro Discrete Library to Agilent ADS Translator offsets in the CDNSsymbo.iff 1096613 ALLEGRO_EDITOR INTERACTIV Enh-While moving parts silk ref des should remain visible 1096676 CONCEPT_HDL CORE SPB 16.5 HF36 breaks designs that workded fine in HF35 1096913 APD IMPORT_DATA Import > NA2 fails to bring in the Y1 component. 1097751 ALLEGRO_EDITOR DATABASE Import CIS netlist crashes. 1097889 ALLEGRO_EDITOR DRC_TIMING_CHK Allegro crashes when routing from a via to a pin using High Speed option license.