Cadence Encounter Digital Implementation v12 Cadence® Encounter® Digital Implementation (EDI) System provides the most effective methodology to maximize performance, and minimize area and power for high-performance, giga-scale designs. Integration with the Virtuoso® custom design environment ensures seamless data transfer and increases productivity for mixed-signal designs. EDI System also supports advanced 20nm process technologies and system-in-package/3D-IC design. With these capabilities, EDI System delivers the most comprehensive solution for physical implementation of today’s most demanding designs. Benefits Predictability and convergence Combines full-chip implementation with in-design signoff analysis in a single environment Enables design exploration and accurate chip feasibility analysis, including automated floorplan synthesis and ranking, as well as hierarchical budgeting and planning for convergent hierarchical implementation results New GigaOpt and CCOpt engines deliver better power, performance, and area results for high-performance designs, allowing block implementation to meet and exceed aggressive goals Achieves faster, more convergent timing closure by using same extraction engine during in-design and signoff Supports comprehensive multi-mode/multi-corner analysis and optimization in all steps throughout the flow Supports location-based on-chip-variation technologies and the latest methodologies for statistical timing and leakage analysis and optimization Productivity and faster time to market Supports hierarchical methodologies including bottom-up block-based flows, top-down black-box flows, and hybrid flows with partitioning and time budgeting GigaFlex technology adapts to growing capacity requirements while still retaining the relevant timing, placement, and congestion information to accurately plan and implement giga-scale designs FlexModels provide up to 90% netlist compression and an optimized interface for accurate design exploration and planning, resulting in faster turnaround time and one-pass implementation handoff FlexILMs and FlexViews enable concurrent top- and block-level implementation and closure for hierarchical designs; more transparent hierarchical abstraction; and fewer iterations during top-level optimization and assembly Supports a constraint-driven mixed-signal environment through the OpenAccess database, allowing for concurrent custom/digital design methodologies with smoother transitions between Virtuoso and Encounter environments Performs fast and accurate optimization and analysis in the flat physical implementation flow by leveraging the new multi-CPU/multi-threaded–enabled Advanced Analysis Engine for single-step timing and signal integrity delay calculation Delivers signoff-driven analysis during design implementation including multi-mode/multi-corner signoff ECO, as well as intuitive visual features for global timing, power, signal integrity, and clock tree diagnostics Scalability in performance Delivers industry-leading performance and capacity for large, complex chips Offers a complete, end-to-end, multi-core parallel processing backplane and infrastructure Provides best-in-class, efficient multi-corner functionality to significantly improve turnaround time Differentiated product development with lower production costs Includes comprehensive support for 28/20nm designs to handle design scale and complexity as well as new DFM requirements Supports 20nm double-patterning physical implementation and signoff requirements, from placement and routing to timing, power, and physical signoff Enables concurrent chip/package co-design and optimization with integrated capabilities such as automatic area and peripheral I/O placement and flip-chip RDL routing Allows floorplanning, implementation, and analysis of 3D stacked-die designs with through-silicon-via (TSV) connectivity for optimization of heterogeneous processes/dies, ensuring fewer iterations and faster convergence with in-design 3D-IC signoff extraction and timing/power analysis across multiple dies