Cadence spb 16.30.011 hotfix


Filed under: PCB Layout and routing, PCB design, SPB, Allegro PCB Editor, Constraint Manager, via, PCB Editor, PCB, SPB 16.3, Allegro 16.3, "PCB design", SPB16.3 Current design technologies require extremely tight matching requirements right down to the overall net topologies to ensure that any deviations in propagation delays are minimized. As a result, design guidelines call for matching the number of vias for a group of signals. The prior releases of Constraint Manager support a "MAX_VIA_COUNT" constraint which does not meet the needs of these new design requirements. The SPB16.3 Allegro PCB Editor constraint system now supports a method to check for an equal number of vias in addition to a "maximum" number of vias on a group of nets or pin pairs. Also, prior to the SPB16.3 release, if the Max Via constraint was applied to both nets of an Xnet, the most conservative value would ascend up to the Xnet level. This essentially prevents the control of vias on each side of the pass through device. A behavioral change has been made to the Max Via rule that maintains the constraint values at the net level. If constraining at the Xnet level is desired, the constraint will need to be explicitly applied to it. Read more details below


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