Encounter Timing System serves both front-end logic designers looking for high-quality, high-throughput timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff. With Cadence® Encounter® Timing System, designers benefit from a consistent, integrated, multi-CPU enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence. Encounter Timing System helps designers analyze and debug multimillion-gate designs with significant gains in productivity. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and performance. Using the effective current source model (ECSM) for advanced timing, power, signal integrity (SI), and statistical delay modeling, Encounter Timing System delivers the most accurate prediction of actual silicon performance and shaves weeks off tapeout schedules, giving designers a competitive edge over traditional delay modeling. Features/Benefits * Delivers consistent, integrated STA, SI, and statistical static timing analysis (SSTA) for optimization and signoff * Eliminates the need for multiple products by integrating timing, SI, power, thermal, and SSTA analyses * Global timing debug speeds up root-cause and bottleneck analysis * Accurate and advanced analysis algorithms reduce false SI failures by 10x * Parallel processing leverages multi-CPU and distributed servers for faster throughput * Performs concurrent multi-mode/multi-corner analysis with distributed processing * Enables advanced nanometer design through ECSMs * Delivers accurate delay calculation to within 2% of SPICE * Offers built-in critical path simulation for delay/SI correlation with SPICE