With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design for manufacturability and yield, low-power and mixed-signal design support, and nanometer routing. It also offers the latest capabilities to support advanced 65nm and 45nm designs. Features/Benefits * Supports multiple implementation styles with built-in power-planning, floorplanning, and signal integrity analysis * Supports multiple methodologies for flip-chip implementation, promoting concurrent chip/package design * Provides a statistical static timing analysis solution and standardized ECSM library models * Incorporates cutting-edge yield and low-power design capabilities * Handles 50M+ gate designs at 90nm and below