Cadence Incisive Enterprise Specman Elite Testbench (SPMN) 6.0 Linux

Description

Cadence® Incisive® Enterprise Specman Elite® Testbench uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its functional coverage analysis capability drives verification using the Plan-to-Closure Methodology. Specman technology also supports industry-standard verification languages, compatible with both the Open Verification Methodology (OVM) and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. With the Enterprise System-Level (ESL) Option, Specman technology can be extended to support hardware/software co-verification with pure software simulation-based flows as well as complete “in-system” flows via high-speed links to acceleration and emulation. Features/Benefits * Captures executable specifications to eliminate misrepresentations that can lead to bug escapes * Leverages the e language’s unique aspect-oriented programming (AOP) capabilities for rapid environment construction, scalability, and reuse * The “IntelliGen” AOP constraint solver automates test generation with up to 5x faster runtime, unprecedented distribution control, and scalability for more than 1 billion logic gate devices * Automates data and assertion checking for fast debug * Tracks industry-standard functional coverage metrics (functional, transactional, and HDL code) for higher verification quality * Rapidly configures existing reusable Universal Verification Components (UVCs) or quickly constructs all-new UVCs for even greater productivity * Creates reusable sequences and multi-channel virtual sequences on top of an e verification environment * Comprehensive language support includes e, Open Verification Library (OVL), OVM class library, SystemC®, SystemC Verification Library, SystemVerilog, Verilog®, VHDL, PSL, SVA, C/C++ models, MATLAB models, and analog models in Verilog-A, VHDL-A, and SPICE

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