Cadence IUS (Incisive unified simulator) 8.2 USR1 Linux , part of the Incisive platform, provides everything you need to verify today's toughest designs. Its single-kernel architecture natively supports Verilog, VHDL, SystemC, SystemC Verification library (SCV), and PSL/Sugar assertions. Incisive includes a comprehensive verification environment including full transaction-level support and unified test generation. You can extend Incisive with other elements of the Incisive platform including Acceleration-on-Demand with Incisive XLD, analog/mixed signal/RF verification using Incisive AMS, and algorithm development and verification using Incisive SPW.

Key Features:

• Offers the ultimate simulation-based speed and efficiency
• Provides 100x RTL performance through native transaction-level simulation
• Reduces testbench development up to 50% with transaction-level support, unified test generation, and verification component reuse
• Decreases debug time up to 25% through unified transaction/signal viewing, native assertion support, and unified debug environment for all languages
• Increases RTL performance by 100x with optional Acceleration-on-Demand