Description
Cadence® Incisive® Enterprise Simulator (IES) 8.0 automates testbench generation, reuse, and analysis to verify designs from the system level, through RTL, to the gate level. Its metric-driven approach supports a coverage-driven methodology, from verification planning to closure. Its native-compiled architecture speeds the simultaneous simulation of behavioral, transaction-level, RTL, and gate-level models, eliminating the performance degradation often seen in other co-simulation approaches.
Incisive Enterprise Simulator also supports all IEEE-standard languages, the Open Verification Methodology (OVM), and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. Verification engineers can extend the functionality of Enterprise Simulator with the Enterprise System-Level (ESL) Option, which provides a high-throughput channel between the testbench and the device under test (DUT), and enables automated Plan-to-Closure verification of embedded software exactly as if it were another part of the DUT.
Incisive Enterprise Simulator also supports all IEEE-standard languages, the Open Verification Methodology (OVM), and the e Reuse Methodology (eRM), so engineers can quickly and easily integrate it with established verification flows. Verification engineers can extend the functionality of Enterprise Simulator with the Enterprise System-Level (ESL) Option, which provides a high-throughput channel between the testbench and the device under test (DUT), and enables automated Plan-to-Closure verification of embedded software exactly as if it were another part of the DUT.
Features/Benefits
- Automates testbench generation, analysis, and reuse for increased productivity
- Ensures verification quality by tracking industry-standard coverage metrics, including functional, transactional, and HDL code, plus automatic data and assertion checking
- Drives and guides verification with an automatically backannotated and executable verification plan
- Creates reusable sequences and multi-channel virtual sequences on top of a multi-language verification environment
- Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs
- Supports e, the Open Verification Library (OVL), the OVM class library, SystemC®, the SystemC Verification Library, SystemVerilog, Verilog®, VHDL, PSL, SVA, and the Si2 Common Power Format (CPF)
- Delivers the highest possible performance for mixed-language designs, across multiple levels of abstraction, including the ability to “hot swap” the software simulation in/out of the Incisive Xtreme® series of accelerators/emulators