Found 7 query results that match Aldec

  • Aldec ALINT-PRO 2021.09

    Aldec ALINT-PRO 2021.09 Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has launched ALINT-PRO 2021.09 is design rule checking (DRC) tool, which decreases development time dramatically by identifying design issues early in the .....
    Language : english Authorization: Pre Release Freshtime：2022-02-10 Size: 1DVD

  • Aldec Riviera-PRO 2017.02_ Functional Verification

    Aldec Riviera-PRO 2017.02 Functional Verification Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engin.....
    Language : english Authorization: Pre Release Freshtime：2017-11-13 Size: 1CD

  • Aldec.Riviera-PRO.2015.02.76

    Functional Verification Verification-Platform-Grows-01.jpgRiviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulatio.....
    Language : english Authorization: Retail Freshtime：2015-04-02 Size: 1CD

  • Aldec Active HDL 8.2 With UPDAT3

    ctive-HDL 8.2.1986 Update 3 Update 3 contains: A. changes and improvements from Update 1: A.1. Support for Xilinx ISE 11.2 in the Design Flow Manager A.2. Support for new ISE 11.2 families and devices in the Synopsys FPGA C-2009.06 (Synplify) flowchart A.3. Support for new ISE 11.2 in .....
    Language : english Authorization: Pre Release Freshtime：2009-11-20 Size: 808MB

  • Aldec Riviera-PRO 2009.02

    Aldec, Inc., announced today the release of Riviera-PRO 2008.06, a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C+.....
    Language : english Authorization: Pre Release Freshtime：2009-11-08 Size: 143.8MB

  • Aldec ALINT 2009.02

    ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, clock and reset issues prior to simulation and synthesis. Powerful, g.....
    Language : english Authorization: Retail Freshtime：2009-11-08 Size: 97MB

  • Aldec Active-HDL 8.1

    FPGA Design "Made easy" Active-HDL™ is a Windows® based integrated FPGA Design and Simulation solution. Active-HDL includes a full HDL graphical design tool suite and RTL/gate-level mixed-language Simulator. The design flow manager evokes 80 plus EDA and FPGA tools, during design, simulation, synt.....
    Language : english Authorization: Retail Freshtime：2008-10-09 Size: 818MB