ALINT™ is an RTL design analysis tool that identifies design issues early in the development cycle. VHDL, Verilog® or mixed-language designs are checked for coding inconsistencies, design structure issues, synthesis, simulation, clock and reset issues prior to simulation and synthesis. Powerful, graphical utilities are provided for violation analysis and debugging. ALINT significantly reduces verification time for complex FPGA and ASIC designs, which results in uniform, reusable and reliable code, reducing the risk of costly ASIC re-spins. Comprehensive rule sets are available for VHDL, Verilog and mixed-language designs. User-definable rules and extensive rule management features enable corporate standardization. Top Features * Fast design analysis of complex ASIC/FPGA/SOC designs * IEEE VHDL, Verilog and mixed-language designs * STARC VHDL or Verilog rule plug-ins * DO-254/ED-80 VHDL or Verilog rule plug-ins * RMM rule plug-in * Custom rule creation * Integrated result analysis and debugging environment