Cadence® Incisive® Enterprise Specman Elite® Testbench uses executable specifications and designer-specified constraints to automate testbench generation, while simultaneously detecting misrepresentations of the specification. Its automated data and assertion checking speeds debug, while its fun.....
Language : english Authorization: Retail Freshtime：2008-09-09 Size: 689MB
Cadence® Incisive® Formal Verifier allows design teams to start RTL block verification months earlier than when using traditional simulation-based techniques. Its formal, assertion-based approach and exhaustive analysis capabilities ensure verification quality by pinpointing the source of bugs and.....
Language : english Authorization: Retail Freshtime：2008-09-09 Size: 734MB
Incisive Desktop Manager Automated verification managementIncisive Desktop Manager automates and guides the everyday deployment and visualization of verification tasks and results, increasing engineering productivity and reducing time to market.Cadence® Incisive® Desktop Manager accelera.....
Language : english Authorization: Retail Freshtime：2008-09-09 Size: 397MB
Synopsys Liberty NCX 2008.06 sp2 Linux-- The Fastest Path to Production Current-Source LibrariesSynopsys推出了其库编译器的升级版本，新增了对该公司复合电流源(CCS)模型的支持。该公司还推出了基于CCS的新型库特征化工具集Liberty NCX。Library Compiler接受开放源Liberty库格式，并将其编译到Synopsys工具的库内。.....
Language : English Authorization: Retail Freshtime：2008-09-08 Size: 45MB
在采用现有 IP核创建系统级芯片(SoC)时，关键是在设计周期之初，在目标环境中快速地配置和验证IP核。在采用多个IP模块和诸如AMBA的芯片级总线进行设计创建时，设计人员需要能够轻易地完成将多个IP模块连接到总线上并进行配置，从而能够将精力集中在设计中新的逻辑电路上。采用了DesignWare IP 重用工具，IP的创建者可以将自己的IP.....
Language : English Authorization: Retail Freshtime：2008-09-08 Size: 44MB
PCBM Matrix IPC-7351A LP Wizard 2009 是IPC7351标准的PCB封装（footpoint/cell）生成工具，用于生成符合DFM要求的PCB封装符号。::::::English Description::::::The IPC-7351A LP Wizard is a fantastic time saver. It is a land pattern calculator based on the IPC-7351A SMT land pattern standard that allows you to .....
Language : English Authorization: Retail Freshtime：2008-09-05 Size: 0KB
TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It's the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys' patented DFTMAX™ compression the leading test synthesis tool. The unparalleled ease-of-use and high performanc.....
Language : english Authorization: Retail Freshtime：2008-09-05 Size: 117MB
The main HFSS interface is shown in Figure 1, which illustrates the main components of the
gui. They are summarized as follows:
• 3D Modeler Window This is the area where you create the model geometry. This
window consists of the model view area (or grid) and the history tree as shown in
Figure 2. .....
Language : english Authorization: Retail Freshtime：2008-09-04 Size: 418MB
The Cadence® AMS Methodology Kit employs the
Cadence Advanced Custom Design (ACD) methodology,
which leverages silicon-accurate design methods to
enable design teams to create differentiated silicon faster
and with less risk. The kit delivers verified, packaged
methodologies (demonstrated on a real.....
Language : english Authorization: Retail Freshtime：2008-09-04 Size: 870MB
General verification tips:
– Take advantage of the different compare efforts (Low,
Med, High, Super, Ultra, Complete).
– Handling cell libraries – verify first the library cells and
then use one view for both golden and revised.
– LEC parallel compare enables us to reduce the
memory load per mac.....
Language : english Authorization: Retail Freshtime：2008-09-04 Size: 206MB
Pioneering PC based workstation simulation, Intusoft introduced its original IsSpice simulator in 1985. Now, several generations of simulation technology later, the 4th generation IsSpice4 simulator combines Berkeley SPICE 3 (Simulation Program with Integrated Circuit Emphasis) analog simulation wit.....
Language : english Authorization: Retail Freshtime：2008-09-04 Size: 30MB
With the Cadence® SoC Encounter™ RTL-to-GDSII System, engineers can account for the effects of interconnect across the entire chip—from the outset of the implementation cycle. It combines RTL synthesis, silicon virtual prototyping, automated floorplan synthesis, clock network synthesis, design fo.....
Language : english Authorization: Retail Freshtime：2008-09-03 Size: 1.98G
EXT91 is ok for use with ASSURA32USR2_HF and above but some features such as the usage of a non-existent net "0" as the ground net requires ASSURA41_HF3 and above. As ASSURA32 is quite out-dated, please download the latest version of Assura41. I would also think that it is better to upgrade to IC614.....
Language : english Authorization: Retail Freshtime：2008-09-03 Size: 520MB
Analog/mixed-signal extractor; provides high-speed parasitic extraction on full-chip layouts with silicon accuracy; part of the silicon analysis function inside the Virtuoso® custom design platform
..
Language : english Authorization: Retail Freshtime：2008-09-03 Size: 1.43G
Encounter Timing System serves both front-end logic designers looking for high-quality, high-throughput timing analysis and ease of use, as well as back-end implementation engineers requiring electrical analysis and a common timing engine for silicon-accurate signoff.
With Cadence® Encounter® Tim.....
Language : english Authorization: Retail Freshtime：2008-09-02 Size: 575MB
Cadence IUS is the Incisive Unified Simulator which is used in classes such as ECE130 and CSSE232. This software allows you to perform behavioral simulation on Verilog and VHDL code. ..
Language : english Authorization: Retail Freshtime：2008-08-31 Size: 1.81G
SIMetrix and SIMPLIS
SIMetrix is a mixed-mode circuit simulation package designed for professional electronics engineers. SIMetrix comprises a substantially enhanced SPICE simulator, schematic editor and waveform viewer in a unified environment.
SIMetrix/SIMPLIS is an advanced software tool that e.....
Language : english Authorization: Pre Release Freshtime：2008-08-26 Size: 87MB
The following sections describe known issues at the time of the DSP Module 8.6 release.
* The Show Implementation feature of the following DSP-specific Express VIs does not find DSP-specific subVIs: Simulate Signal, Sweep Generator, Spectral Measurements, Filter, and DFD Filter.
* When usin.....
Language : english Authorization: Retail Freshtime：2008-08-14 Size: 253MB
::::::English Description:::::: The National Instruments LabVIEW System Identification Toolkit combines data acquisition tools with system identification algorithms for accurate plant modeling. You can take advantage of the LabVIEW intuitive data acquisition tools such as DAQ Assistant to stimulate.....
Language : english Authorization: Pre Release Freshtime：2008-08-14 Size: 574MB
National Instruments LabVIEW SignalExpress provides an interactive measurement workbench for quickly acquiring, analyzing, and presenting data from hundreds of data acquisition devices and instruments, with no programming required. Use the intuitive drag-and-drop environment to instantly acquire dat.....
Language : english Authorization: Retail Freshtime：2008-08-13 Size: 624MB