Synopsys Formality 2010.03 Linux

Description

Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all of the out-ofthe- box DC Ultra optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs. Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time. PDFDownload Datasheet Key benefits * Perfect companion to DC Ultra – supports all DC Ultra default optimizations * Intuitive flow-based graphical user interface * Verifies low-power designs including power-up and power-down states * Auto setup mode reduces “false failures” caused by incorrect or missing setup information * Built-in distributed verification boosts performance * Automated guidance boosts completion with DC Ultra * Verifies full-custom and memory designs when including ESP technology The most comprehensive equivalence checking solution Formality delivers superior completion on designs compiled with DC Ultra, which uses Topographical Technology to achieve accurate correlation with post-layout timing, area and power, and provides advanced optimizations such as retiming, phase inversion and ungrouping. Formality is also fully compatible with DC Graphical used to predict and alleviate routing congestion. Designers no longer need to disable DC Ultra’s powerful optimizations to get equivalence checking to pass. DC Ultra combined with Formality delivers maximum Quality of Results (QoR) that is fully verifiable.

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