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- Language：english
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- Freshtime：2018-10-25
- Search：Synopsys Synplify Premier 2018.3 Synopsys Synplify 2018.3 training tutorials
Description
Synopsys Synplify Premier 2018.3
Synplify Premier
Accelerate Implementation of FPGA Designs and FPGA-based Prototypes
Synplify Premier® is the industry's most advanced FPGA design and debug environment. The Synplify synthesis tools provide fast runtime, performance, area optimization for cost and power reduction, multi-FPGA vendor support, incremental and team-design capabilities for faster FPGA design development. Synplify Premier includes features that automate the creation of highly reliable designs such as those used in medical, automotive, industrial automation, communications, military and aerospace applications.
The Synplify Premier features:
- Automated gated clock conversion for FPGA-based prototyping support
- Integrated Identify RTL Debugger to quickly find functional errors
- Automated design for high reliability and safety-critical design including DO-254, ISO 26262 and IEC 61508
- Integration with VCS Simulator and direct support for DesignWare IP
- Best quality of results (QoR) for timing performance and area/cost reduction
- Distributed synthesis with support for single or multiple machine synthesis
- Accelerated runtimes delivering up to 3X runtimes with support for up to 4 processors per license
- Automatic memory and DSP inference provides optimal area, power and timing quality of results
- Broad language support with VHDL, Verilog, SystemVerilog, VHDL-2008 and mixed language synthesis
- Advanced design debug and diagnosis through HDL Analyst and hierarchical debug flows