Synopsys IC Compiler 2009.06 SP5 Linux new release.
IC Compiler - A Comprehensive Solution
IC Compiler uses Extended Physical Synthesis (XPS), a significant capability that extends physical synthesis to full place-and-route. XPS enables faster turnaround time (TAT) as well as better QoR, measured in terms of the complete cost vector — timing, area, power, signal integrity, routability, and yield.
IC Compiler is tightly correlated to the industry-standard signoff solutions—PrimeTime® SI and StarRC™. Additionally, it utilizes these signoff engines to achieve fast, accurate signoff driven design closure during the final changes of physical design implementation. Signoff driven design closure further increases design predictability.
IC Compiler provides a comprehensive DFM solution that concurrently optimizes for yield with timing, area, power, test, and routability. IC Compiler increases manufacturability of the design, optimizing both functional and parametric yield.
IC Compiler with concurrent hierarchical design enables powerful design planning and chip-level analysis features to handle large, complex designs. Providing early analysis and feasibility exploration, IC Compiler delivers smaller die size and achieves predictable design closure to reduce the cost of design.
IC Compiler with Zroute technology utilizes advanced routing algorithms, concurrent DFM optimizations and multithreading to deliver a combined speed increase of more than 10X in routing.