Synopsys, Inc. has released Synopsys Core Synthesis Tools vX-2026.03 is a software that takes VHDL descriptions as input and generates circuits composed of gates, flipflops, and registers based on specified synthesis constraints.

Synthesis, within the field of electronic design automation (EDA), is the automated process of transforming high-level hardware descriptions into lower-level representations that can be physically manufactured on a semiconductor chip. Most commonly, synthesis refers to converting Register Transfer Level (RTL) code, written in hardware description languages like Verilog or VHDL, into a gate-level netlist.

Synthesis provides a bridge between the abstract, human-readable logic that designers create and the concrete, detailed hardware that manufacturing tools require. It is a crucial step for ensuring that the intended functionality, performance, and other design goals are maintained when moving from concept to physical device.

Synthesis not only translates code but also optimizes the resulting circuit for key metrics such as power consumption, performance (speed), and silicon area. As technology nodes become smaller and designs more complex, synthesis plays an increasingly important role in making sure chips are efficient, reliable, and manufacturable.

All Synopsys synthesis tools support industry-standard hardware description languages such as Verilog, SystemVerilog, and VHDL. By adopting these solutions, engineering teams can accelerate convergence, gain early insight into design quality, and achieve competitive results in both FPGA and ASIC design.