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Description
Synopsys Hspice vY-2026.03
Synopsys HSPICE vY-2026.03 is the latest release of the industry's gold-standard circuit simulator, trusted by semiconductor designers and foundries worldwide for accurate SPICE-level verification of analog, mixed-signal, and RF integrated circuits. As a cornerstone of the Synopsys Discovery AMS verification solution, it delivers unmatched accuracy for timing, power, and noise characterization across advanced process nodes.
What's New in HSPICE vY-2026.03
Performance & Accuracy Enhancements
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Up to 20x runtime improvement for transient analysis through enhanced time-step control algorithms
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Simplified simulation control interface with single-option tolerance scaling, eliminating manual adjustment of multiple settings
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Automatic time-step maximization to meet desired accuracy levels while minimizing simulation time
RF & High-Frequency Design Support
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Harmonic balance engine for periodic steady-state (PSS) analysis, periodic noise, phase-noise, and periodic AC analysis
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Support for 8,000+ transistors in RF block-level simulation for wireless transceivers, WLAN, and cellular applications
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Golden-accuracy convergence for high-frequency nonlinear circuits
Foundry-Certified Models
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Comprehensive foundry-certified device models for accurate library characterization
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Enhanced noise analysis capabilities with significant performance improvements for power and signal integrity verification
Core Features
Analog & Mixed-Signal Simulation
Industry-leading SPICE accuracy for DC, AC, transient, and noise analysis of complex analog circuits including operational amplifiers, data converters, PLLs, and voltage regulators.
Digital & Memory Verification
Fast and accurate simulation of digital logic, SRAM, DRAM, and flash memory cells with advanced convergence algorithms for large-scale mixed-signal designs.
Power Analysis
Comprehensive power consumption analysis including dynamic power, leakage power, and switching activity for low-power design optimization.
Signal Integrity
Advanced crosstalk, ground bounce, and substrate noise analysis for high-speed interconnect and I/O design in advanced packaging technologies.
Monte Carlo & Corner Analysis
Statistical simulation for process variation analysis, yield optimization, and design centering across temperature, voltage, and process corners.
Custom Model Support
Extensible model interface supporting Verilog-A, C-language models, and proprietary foundry models for emerging device technologies.
Integration & Workflow
Seamless integration with Synopsys Custom Compiler, PrimeSim, and WaveView for complete analog/mixed-signal design and verification flows.