Mentor Graphics Olympus-SoC Digital IC Design 2009.04

  • Size：180MB
  • Language：English
  • Platform：/Linux
  • Freshtime：2009-10-10
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Description

Mentor Graphics IC implementation solution, Olympus-SoC™, delivers innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes

The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization. It also includes litho-driven routing that addresses optical proximity correction (OPC), resolution enhancement technology (RET), and critical area analysis (CAA) early in the design cycle, ensuring faster timing closure for complex process rules.

Benefits of Olympus tools:

  • Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization
  • Reduce power consumption in clock trees with MCMM clock tree synthesis
  • Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation
  • Speed time-to-market with fewer design iterations, scalable multi-threading, and sign-off quality closure
  • Load and process designs of 100M gates or more with the industry's highest-capacity data structure
  • Reduce costs through high yields and fast time-to-market

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