Core Capabilities of Catapult HLS

The platform is built around several key features that address the major challenges in modern chip design:

• Algorithmic Design & Verification: By raising the design abstraction from RTL to C++/SystemC, designers can focus on the algorithm itself. This approach can reduce coding effort by up to 80% and speed up simulation by thousands of times compared to traditional RTL methods .

• C++ and SystemC Support: Catapult natively supports both C++ and SystemC, offering flexibility for different design needs. SystemC allows for more precise modeling of hardware behavior, such as concurrent processes and interface protocols, which is critical for complex SoC designs .

• Power, Performance, and Area (PPA) Optimization: The tool addresses PPA trade-offs early in the design cycle. It includes features like physically-aware multi-Vt optimization for area and static power, and integrates PowerPro technology for power estimation and optimization at the architectural level .

• High-Level Verification (HLV): Verification is a major bottleneck in chip design. Catapult's HLV platform allows for verification at the C++/SystemC level, which is much faster than RTL simulation. It is claimed this can reduce RTL verification costs by up to 80% .

• AI-Driven Exploration: The newer Catapult AI features help accelerate design space exploration by predicting PPA outcomes for different micro-architectural choices, enabling designers to find optimal solutions more quickly .