• New and enhanced DSP library functions, AI Engine APIs, and support for new data typesg

Versal AI Core Series with AIE​:

• Enhanced GEMV & FFT for AI Engine using 2D parallel AIE + programmable logic (PL) architecture (suitable for polyphase channelizer)
• Vectorized bitonic SIMD sorting, correlation, convolution

Versal AI Edge Series with AIE-ML​:

• FFT for AIE-ML using 2D parallel AIE-ML + PL architecture (suitable for polyphase channelizer)
• Vectorized bitonic SIMD sorting, correlation, convolution

Versal AI Edge Series Gen 2 with AIE-ML v2:

• 2D FFT AIE-ML v2 + PL v1 (suitable for polyphase channelizers)
• TDM FIR (suitable for polyphase channelizers)
• GEMM / GEMV
• Single-rate FIR
• Half-band FIR
• Fractional resampler FIR
• Rate change FIR
• FFT/iFFT
• DFT
• DDS mixer
• Function approximation

AI Engine Programming Updates:

• Tiling parameter specifications for local memory
• Reduced compile times when changing testbench
• Faster pipelining for design using ping-pong buffers in DDR in AIE-ML
• Other memory access enhancements in AIE-ML

Easier Verification of Versal AI Engine Designs

• Functional simulation of Vitis subsystems in MATLAB® & Python™
• Enhanced latency and throughput measurement support in Vitis Analyzer – for AI Engine designs
• Runtime control of independent AIE partitions 

Enhancements to Vitis Model Composer for AIE DSP Designs

• Support for multiple top-level AI Engine subsystems
• Additional blocks available for both AIE and HDL, including enhanced FFT with additional SSR modes and complex multipliers that can use fewer  DSP58 resources 

Updates for Vitis IDE for Embedded Development

• Vitis Unified IDE (New GUI) will be default - Classic Vitis IDE is deprecated
• Third-party tool chain support such as GCC and ARMClang
• Third-party productivity tools can now be installed and accessed through a marketplace utility within Vitis IDE