TetraMAX ATPG Automatic Test Pattern Generation Overview TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys’ patented DFTMAX™ and DFTMAX Ultra, the leading test synthesis tools. The unparalleled ease-of- use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compressed test patterns for even the most complex designs. Key Benefits Improves product quality with comprehensive fault model support and power-aware test patterns Increases designer productivity by leveraging integration with Synopsys test compression tools Generates test patterns for even the largest and most complex SoCs Enables faster yield ramp by quickly isolating defect locations Features Extremely high capacity and performance Multicore support for accelerated run time Integrated graphical user interface, hierarchy browser and simulation waveform viewer Comprehensive scan and compression design rule checking Integrated fault simulator for grading structural test patterns Silicon diagnostics with automatic defect isolation Options TetraMAX DSMTest option enables advanced fault models and power-aware patterns TetraMAX IDDQ Test option available for quiescent test validation Integrated with Synopsys Yield Explorer for seamless volume diagnostics and yield analysis Testing Complex ASICs With TetraMAX ATPG, designers can generate high-quality manufacturing test patterns without compromising on high performance design techniques (Figure 1). While such techniques may impede other ATPG tools, TetraMAX ATPG is able to obtain coverage on the resulting complex logic. TetraMAX ATPG supports internal three-state busses including implementations with pull-ups, pull-downs and charge storage. Similar to three-state busses, bidirectional I/O pads are also supported. To ensure ATE (automatic test equipment) requirements are met, TetraMAX ATPG provides a number of options to generate contention-free patterns for three-state logic.