Comprehensive Place and Route System Overview IC Compiler is the leading place and route system. A single, convergent, chip-level physical implementation tool, it includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs at all process nodes. IC Compiler is the industry leading place-and-route system for established and emerging process technology node designs. Multicore support throughout the flow delivers improved productivity. New technologies, like concurrent clock and data (CCD) with clock concurrent optimization, PrimeTime physically-aware engineering change order (PT-ECO) guidance with minimum physical impact implementation, and golden unified power format (IEEE 1801 UPF), enable designers to handle gigascale design complexity and meet tight project schedules. IC Compiler hierarchical design technology enables powerful design planning and early chip level exploration / analysis features to handle large, complex designs. IC Compiler delivers smaller die size with predictable design closure to reduce the cost of design. IC Compiler with Zroute digital router technology utilizes advanced routing algorithms, concurrent manufacturability optimizations and multi-threading, to improve manufacturability and deliver faster turn-around-time. IC Compiler In-Design technology seamlessly integrates the IC Validator signoff DRC and metal fill solution allowing designers to mitigate manufacturing compliance challenges in the implementation stage for faster signoff closure. IC Compiler is the cornerstone of the Galaxy™ Design Platform and is tightly correlated to the industry-standard signoff solutions – PrimeTime® SI and StarRC™ with value links to Design Compiler® Graphical. Benefits IC Compiler delivers all the technology required to realize both mainstream and advanced designs at any process node, from the established nodes still in use (e.g., 0.35μm, 0.25μm, 180nm, 130nm, 90nm, 65nm, 45nm) to the latest emerging process nodes at 20nm and below. IC Compiler is the leading physical implementation tool and is uniquely positioned with value links to Design Compiler Graphical®, PrimeTime SI, StarRC, IC Validator, Custom Designer, the Galaxy Custom Router, and PrimeRail. Beyond value links, IC Compiler shares technology with and correlates to Design Compiler Graphical, PrimeTime SI and StarRC to ensure a fast and monotonic path from design to final signoff. Additionally, IC Compiler In-Design technology enables early physical verification and fixing using IC Validator technology and accurate foundry runsets. IC Compiler benefits the physical designer in four key categories: Quality of Results, Turn-around Time, Ease of Use, and Cost of Design. Quality of Results Innovative multicorner multimode (MCMM) and multivoltage (MV) technologies in IC Compiler digital implementation system delivers improved QoR, measured in terms of the complete cost vector – timing, area, power, signal integrity, routability, robustness and manufacturability. Physical datapath: Physical datapath technology allows designers to create regular placement structures by specifying constraints for the relative row and column positions of cell instances. Figure 2 highlights some of the benefits of physical datapath. User controlled data element array packing leads to better timing and routing predictability. By using physical datapath designers also lower power and reduce die area.