Synopsys coreTools IP Based Design and Verification Overview The Synopsys family of coreTools is a comprehensive set of intellectual property (IP) packaging and integration tools for use in a knowledge-based design and verification flow. The tools enable designers to realize maximum productivity gains when using IP in their desing. By using an IP-based design and verification flow with IP packaged for assembly, the risk configuration, and subsystem integration errors is virtually eliminated, and designers have seen over a 60% reduction in SoC or platform design time and achieve the highest QoR in the implementation of the design. The coreTool family includes: coreBuilder™ – a robust packaging tool that allows designers to capture the knowledge and design intent of the IP and provide graphical or command based configuration menus for the IP. It supports the packaging of all the different model views of the IP needed engineering teams. This reduces IP support costs, improves quality and IP packaged with coreBuilder is fully compliant with the IP-XACT specification. coreAssembler™– an open IP assembly tool that automatically generates the interconnect and configured RTL, as well as documenting the block and system configuration details and design testbench. When combined with coreBuilder, entire subsystems can be packaged as coreKits enabling the easy creation configurable market targeted platforms. In addition to assembly and configuration designers are able to generate a starting testbench configured for the design so they can begin to validate there design. coreAssembler also will generate the IP-XACT XML for the design. coreConsultant™– the utility package for configuring, implementing and validating individual IP blocks packaged with coreBuilder. coreConsultant will also generate the IP-XACT XML for the IP block. Features Intuitive graphical or script-based environment • Built-in interfaces to Synopsys tools, including: • Design Compiler — ® Physical Compiler — ® Power Compiler — ® TetraMA X — ® PrimeTime — ® Formality — ® VCS — ® Automatic testbench generation with DesignWare VIP for • AMBA and AXI which supports VMM and/or traditional testbenches Supports mixed-language HDL designs • Flexible TCL interface for tool customization • Knowledge-based assembly of IP blocks • Full IP-XACT support including TGI with automatic XML • generation Benefits Full support for packaging, integrating, and assembling IP • Allows packaging of IP at multiple levels of abstraction, • including: RTL — Instruction set models — Transaction level models — Bus functional models — Verification test suites — Hard macros — Automatic assembly of pre-designed IP blocks reduces • design time Reduces design integration and support costs