Synopsys SpyGlass vP-2019.06 SP1

Power management techniques, which were once only deployed for wireless applications, have now become ubiquitous. All IC designers now need to configure their RTL for efficient power partitioning along with reduced static and dynamic consumption. This is especially true for more advanced technology nodes. These configurations involve iteratively performing power estimation, profiling and reduction to assess and improve the power efficiency of the design.

Every milliwatt of power matters, regardless of the application. Designers can no longer wait for the final netlist to get accurate power numbers, as full visibility is needed as soon as RTL coding starts, when the most rewarding modifications can be made. At smaller technology nodes, dynamic power is becoming increasingly more dominant and the reduction of overall activity has become a necessity. As designs become vastly larger, designers need a tool that pinpoints the major power gluttons while suggesting modifications with the highest ROI.