Synopsys' Leda® is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda’s pre-packaged rules greatly enhance a designer's ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality. Key Benefits * Finds complex bugs, such as those associated with multiple clock domains using static analysis * Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro * Finds design and coding guideline bottlenecks that impact simulation, synthesis, timing, DFT, ERC, and layout * Enables design reuse with prepackaged guidelines, such as the Reuse Methodology Manual (RMM), DesignWare® and STARC * Implements company specific guidelines by graphically configuring prepackaged rules * Create complex custom rules for syntax, semantic and hardware by reusing source code of the prepackaged rules * Tcl for fast prototyping and C for up to 100X performance when implementing complex hardware rules