Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge™ Antioch™ peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy™ design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation. "For our mobile phone chip design, we needed a solution that could address peak current problems related to the use of Power Gating switches," said Nagendra Cherukupalli, vice president of Asia Pacific design centers and chip integration at Cypress. "Synopsys' PrimeRail and its integration with the Galaxy design platform enabled our designers to analyze power integrity issues of the power gating switches and decoupling capacitors prior to tapeout." Built on Synopsys' gold-standard Star-RCXT™ extraction and PrimeTime® sign-off technologies, PrimeRail offers full-chip analysis, dynamic memory and macro-modeling capabilities for advanced multi-voltage, low-power, high- performance designs. Its multimode analysis capability enables users to pinpoint and mitigate problems with critical power-up rush current or excessive current during wake-up to active mode in MTCMOS designs. PrimeRail is integrated with the Galaxy design platform, allowing designers to predict voltage drop during floorplanning, perform pre- and post-layout analysis with on-chip decoupling capacitance, and achieve full-chip sign-off with package parasitics.