Key Benefits

• Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog
• Accelerates RTL Reuse
• Extensive design checking rules and rulesets
• Interactive HDL visualization and creation tools
• Automatic documentation features and reporting
• Intelligent debug and analysis
• Concurrent design entry and checking

Design and Reuse

• Quickly assess reused code quality and increase design understanding
• Efficiently create RTL designs using text, tables, and graphics
• Interactively manage design flow and all project data
• Rapidly produce documentation
• Accelerate IP repository population

SystemVerilog

• Manage and understand code relationships
• Accelerate language proficiency and results
• Summarize and quantify code characteristics
• Automate and simplify data management
• Design, measure and document for practical code reuse