Means of synthesis of high-performance FPGA-type PLD and FPGA, optimized in terms of ease of use and high quality results. Supports a multi-million-programmable systems-on-Chip (FPSoC) the last generation. Precision RTL Synthesis receive input on the project as a description in VHDL or Verilog and implements logic synthesis with the defined limits, based on built-in libraries of manufacturers. The package has a built-in static timing analysis, the ability to analyze and debug in an incremental mode, and an intuitive user interface makes it easy to manage the process of fusion as an experienced engineer, and beginner. Precision RTL Synthesis includes a unique optimization algorithm - Architecture Signature Extraction (ASE), which automatically selects the most critical in the project area, limiting the overall system performance, such as finite automata, logical paths between the various levels of design hierarchy or logical path with a very large number of combinational logic . ASE algorithm uses heuristic analysis in an automatic mode to reduce the size of the project and increase its productivity without the need for manual intervention. It supports all series of crystals Xilinx (including the Virtex-7), Altera, Actel and Lattice. Year / Date of Release: 2011 Version: 2011a Build 1961 Developer: Mentor Graphics Bit depth: 32bit Compatibility with Vista: complete Compatible with vv!nd0vv$ 7: complete Language: English