Mentor Calypto SLEC 2024 | Sequential Logic Equivalence Checking & High-Level Synthesis Verification Platform

Mentor Calypto SLEC 2024 is an advanced formal verification tool that performs sequential equivalence checking between RTL designs and their high-level synthesis (HLS) or SystemC/C++ source models. It mathematically proves functional equivalence across different levels of abstraction, crucial for verifying HLS and optimizing RTL implementations.

Core Functionality Overview:

• Sequential Equivalence Checking for HLS Flows: Formally verifies that the generated RTL from a high-level synthesis tool (e.g., Catapult HLS) is functionally equivalent to the original C++/SystemC algorithmic source, even in the presence of complex sequential optimizations like pipelining and scheduling.

• Automatic Abstraction & Debug Environment: Automatically abstracts away implementation details (like timing, interfaces) to focus on functional equivalence and provides a powerful debugging environment with counterexample traces for any mismatches found.

• Optimization & Power-Aware Verification: Supports verification of RTL that has been further optimized for power (power gating, clock gating) or area after HLS, ensuring these transformations do not break functional correctness.