L-Edit L-Edit combines industry-leading rendering speed with powerful features and an elegant user interface that delivers unmatched productivity in physical layout. Drawing and editing are done quickly; with fewer keystrokes and mouse clicks than other layout tools. Powerful features such as interactive DRC, object snapping, and alignment work within an intuitive user interface so you can work efficiently and effectively. L-Edit IC Based on L-Edit, the fastest rendering layout editor in the market, L-Edit IC is a comprehensive physical layout and verification system that accelerates design cycles with high performance and an extremely short learning curve. L-Edit IC includes Interactive Design Rule Checking (DRC), Standard Place & Route (SPR), Node Highlighting, Pad Map, Schematic-Driven layout, and our Standard Device Generator. HiPer L-Edit DevGen HiPer L-Edit DevGen is for Engineers looking to gain high productivity by accelerating the task of creating design primitives such as differential pairs, current mirrors, and MOSFETs. This package couples our high-performance L-Edit IC package with HiPer DevGen. Click here to learn more about this high-performance layout acceleration capability. HiPer L-Edit Router HiPer L-Edit Router combines our high-performance L-Edit IC package with our SDL Router; offering unparalleled workflow productivity for engineers doing layout routing. Physical Verification HiPer Verify HiPer Verify from Tanner EDA is a comprehensive yet affordable solution for analog/mixed signal IC design rule checking (DRC) and netlist extraction on the Windows and Linux platforms. HiPer Verify uses advanced hierarchical algorithmic techniques to provide optimal performance for your designs. HiPer Verify can run Calibre and Dracula rule files directly from the foundry; offering the security of knowing you are running your rule files without modification or conversion, as well as the convenience of not having to perform translations.