Actel Designer 8.3

Description

::::::English Description::::::

Designer – Actel s Design Implementation Software

Designer is Actel s powerful physical implementation software tool suite. After completing design entry and functional verification using Libero IDE tools or your favorite front-end design tools, simply import the resulting netlist into Designer to set timing constraints and performing place-and-route, timing analysis, power analysis, and program file generation.

Designer provides full power optimization and analysis tools for Actel s low-power flash FPGA families, including the IGLOO/e 1.2 V devices—the lowest power FPGAs on the market.

Actel s Designer software offers an easy-to-use design implementation solution for all Actel FPGA devices. It gives you the flexibility either use Libero IDE s integrated tools or other EDA tools from partners such as Synplicity, Mentor Graphics, Synopsys, Cadence, and many other top names in the EDA field.

Designer Software Features:

  • Seamlessly compatible with:
  • Support for established EDA standards such as Verilog/VHDL/EDIF/VITAL/SDF/SDC
  • SmartGen correct by construction library of configurable logic and memory cores
  • MultiView Navigator provides physical constraint editing plus cross-probing and other design viewing capabilities with the following tools:
    • ChipPlanner – device-level floorplanning tool
    • PinEditor – package pin assignment tool
    • I/O Attribute Editor – set characteristics of I/O pins
    • NetlistViewer – design schematic viewer
  • Timing- and power-driven place-and-route
  • SmartPower provides comprehensive power analysis features to assist in low power optimization
  • SmartTime static timing analysis and constraints management
  • FlashLock design security programming software
  • Silicon Explorer – real-time debugging software
  • Tcl – commonly used scripting language
  • Actel simulation libraries
  • Supported on Windows, Solaris, and Linux
Designer User Interface

Designer User Interface

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