::::::English Description::::::

While today’s chip designs demand increasing speed and performance, designers are also faced with the challenge of verifying their chips at both analog and logic levels expediently due to shortened product life cycle. Full-chip simulations require prudent setup and tend to create large amount of simulation data to review. Moreover, typical design process involves iterative simulations - a time consuming process.
SPICE Explorer is developed to address the newly arisen necessity for an effective transistor-level debugging environment. The tool is built upon netlist-driven debugging and visualization modules, and WaveView Analyzer with ACE scripting option completes the package. The environment provides front-to-back productivity solutions to speedup verification cycle and reduces total design cost.

Features

• Screens netlist for issues from syntax to design connectivity errors
  
• Finds error early in the verification cycle with comprehensive netlist design checker
• Examines large netlist file of millions of elements in seconds with small memory requirement
• Supports both Hspice and Spectre netlist formats
• Interactive report browser allows designers to pin point problematic devices and setup
• Netlist-driven hierarchy visualization allows intuitive hierarchy traversal
• Stimulus preview capability prior to simulation launch
• Provides interactive editing functions for PWL pattern generation
• WDF mixed-signal waveform compression technology minimizes data size and loading time
• WaveView Analyzer integrated capable of netlist cross-probing
• Analysis Command Environment (ACE) option bundled supporting Tcl/Perl

Supported Platforms

• Sun workstations – Solaris 6, 7, 8, 9, 10
• Intel x86 PC – Microsoft Windows 95/98/NT/XP
• Intel x86 PC – Linux 7.x and above
• HP-UX 11