SPD （Signal Processing Designer）仿真软件是 CoWare Inc.公司的产品，原名为SPW（Signal Processing Worksystem），它提供了面向电子系统的模块化设计、仿真及实施环境，是进行算法开发，滤波器设计，C 代码生成，硬/软件结构联合设计和硬件综合的理想环境。SPW的一个显著特点是他提供了HDS接口和MATLAB接口。MATLAB里面的很多模型可以直接调入 SPW，然后利用 HDS 生成 C 语言仿真代码或者是 HDL 语言仿真代码。
SPD 通常可以应用于无线和有线载波通信、多媒体和网络设计与分析等领域。
它还具有以下技术特点：
1、 高效便捷的仿真手段：它用 C 语言开发，仿真效率高，同时，他提供图形化的配置仿真界面，友好的消息显示机制。而且可以在不需要用户干预的情况下进行多速率、
动态调度的仿真处理。
2、 多种建模方式支持：只要是 C/C++兼容的建模，系统都可以提供支持，其建模参数可以是 C 兼容的变量表达式语言定义的复杂函数。
3、 大规模的标准数据模型，可支持 XML、关系数据库，并提供 TCL、C++等编程接口。 
4、 丰富的构件库，并支持在原有构件库上的编程微调，直接提供 C 源码的编辑和编译环境。
5、 强大的分析和管理工具，可自动生成信噪比曲线，误码率曲线等。
6、 提供从系统建模到芯片级硬件设计的自动化功能。
SPD作为专业的DSP仿真设计开发工具，主要应用在电子设计、通信设计和芯片设计
领域，对移动通信系统也提供了强大的支持，适合做底层开发和仿真。但同OPNET一样，它是一款专业性极强的软件，入门难度较高，同时，作为成熟和专业的商业软件，其价格不菲。

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CoWare Signal Processing Designer
Implementing Algorithms for Platform-Driven ESL Design

Highlights

• Industry s fastest, production proven signal processing simulator
• Fully supported on Windows and Linux
• 4000+ models with source code
• Unique standards reference libraries
• Fully integrated with MATLAB® and Catalytic MCS tools
• Fully integrated into CoWare platform-driven ESL design solution
• RTL cosimulation support for Cadence Incisive® and Mentor Modelsim®
• RTL code generation for Synopsys DesignCompiler® and Cadence Encounter®
• Analog-Mixed Signal (AMS) cosimulation with Cadence Incisive®
• One-click analysis
• Powerful polymodeling capability
• State-of-the-art GUI for maximum productivity
• Scalable XML database
• Automated model migration from SPW designs

Overview
CoWare® Signal Processing Designer (SPD) accelerates the design of complex, digital signal processing (DSP) systems. It is a C-based modeling and simulation environment that facilitates structured modeling and model reuse across design teams. Its efficient creation of complex DSP system models and extremely fast simulation makes Signal Processing Designer the premier choice for today s complex, multi-standard designs in the wireless and multimedia markets. It is tightly integrated with the CoWare Platform Architect and CoWare Processor Designer products.

Value
Designers of today s complex digital signal processing applications face a number of product design challenges which require unique DSP design technology. Optimization of the system cost and power consumption has the biggest impact at the highest abstraction level, where algorithms are created and optimized for the number and complexity of DSP operations needed. Differentiated algorithms determine the user experience with the final product; whether it s the impact of MIMO systems on Long-Term Evolution (LTE) wireless systems or the data rate performance for HSPA or simply the cell phone speech performance. The specific bit-accurate implementation requires not only design skills but specific DSP design tool features to achieve the best quality in the minimum amount of design time. For time to market, compliance to a particular standard is critical, since a non-compliant device is rejected by the system operator. Also, a systematic approach to verification and implementation into hardware and software is important for predicting the time to working product.

The design time and cost are also influenced greatly through a systematic approach to design reuse, which today has to start at the electronic system level (ESL) and cannot be achieved with only some coding rules for C-based modeling.

Solution
Design teams for large digital signal processing systems think in block diagrams when they specify a system. Naturally, CoWare Signal Processing Designer allows capture of the system exactly the same way--in a hierarchical block diagram editor. System designers rely on reuse of fundamental algorithms, while being adapted to specific system requirements through a set of parameters. A large library of 4000+ blocks available for CoWare Signal Processing Designer allows designers to quickly assemble the basic algorithms and set the parameters for a specific application. The way a system designer will evaluate the system performance and optimize it is typically through a large series of long simulations of the system. This requires compilation of the underlying C-models in the complex block diagram and then executing them in a specific order (also called scheduling) to produce the desired outcome. Both the optimal scheduling sequence and the optimization of individual signal processing operations, such as data-type conversions, require sophisticated techniques which are built into the CoWare Signal Processing Designer simulator. If design teams are working on a particular standard, such as HSDPA, they can rely on pre-packaged libraries provided as a reference for the standard. As opposed to individual designers exploring smaller algorithms with MATLAB®, design teams using CoWare Signal Processing Designer are working on total system design, where hundreds of complex individual algorithms have to be integrated, most likely from different designers around the world, today driven by the need for multi-standard, convergence products. Library management and control features help keep the entire design under control and tracking the design evolution as well as facilitating structured reuse of designs. Typical life cycles for important reusable models can span 5-10 years.

After initial optimization of the system using floating-point number representation, the much more involved task of specifying the system at the fixed-point level has to be performed. Customers will make use of the polymodeling feature, which allows the designer to selectively switch between floating and fixed-point representations, without changing the hierarchical block diagram. Reducing the modeling effort to a single model, which can be parameterized across the abstraction levels, is key to reducing the risk for the specification developed. The final fixed-point model is then typically run through a large number of regressions on a server farm in order to check the overall system performance under all available scenarios. Selecting the servers involved and automatically balancing the loads is enabled by configuring the interface to popular load balancing utilities.

Many sophisticated users will model as well at the C-source code level, for example to exactly mimic the production code in an embedded DSP. The interface of a C-function into the CoWare Signal Processing Designer infrastructure is very simple and makes integrating custom code, legacy models or using models as embedded C-code easy. Designers benefit from the available 4000+ models, which all come as source code and can be used as the starting point for modification.

The final verified model serves as bit-exact reference for verification of the system. Any such model can be exported as a peripheral block into a transaction-level SystemC platform into CoWare Platform Architect for usage as reference for system verification. Also, if modeled accurately, any model can be exported as a pin-level SystemC model, which either CoWare Platform Architect or leading RTL simulation products with support for SystemC IEEE 1666. If a specific part of the system is implemented as a custom processor, the processor model generated by CoWare Processor Designer can be integrated into CoWare Signal Processing Designer, thus facilitating the verification of the embedded code running on the processor against the reference model.

Key Features

Getting Started

• Straightforward installation
• Integrated, self-paced tutorial

Simulation

• Fast, compiled, one-click simulation
• Optimizing static scheduler covering wide range of models and variable data length during run-time
• Multi-rate simulation and dynamic scheduling support without user intervention
• Support for server farms running Sun® GridWare, extendable to other load balancing utilities
• Scripting with dynamically changeable parameters
• Statistically equivalent, parallelized bit-error-rate simulations
• User friendly error message connected to cause of errors

Polymodeling

• Common functional models operating with a wide range of different data types
• Packages the power of C++ into a C-based environment with a simple structured modeling approach
• Parameters can be complex functions defined with a C-compliant parameter expression language, supporting the one-model simulation approach
• Built-in source code editor or user-defined external editor

Graphical Design Environment

• Microsoft® Windows style graphical user interface with supported tabbed-design panes for compact design representation and easy navigation
• High connectivity between different design panes eases the tasks of assembling, parameterizing and simulating a system
• Selecting an object in one pane will cause the other panes to select the same object view
• Small number of clicks to perform commonly-used design tasks
• Full flexibility for symbol editing, colors and bitmaps to generate high quality documentation of systems
• Tooltips for instances in designs, models in the library browser and simulation parameters

Scalable Standard Data Model

• Standard XML views for hierarchical models with clean separation of logical and graphical information
• Database scalable for enhancements with more attributes, data type and parameters for future design flow requirements
• Multiple, static manipulations and analysis of the database can be performed through Tcl and C++ programming interfaces; useful for corporate design methodology teams

MATLAB Integration

• MATLAB functions can be integrated through automated calls to MATLAB engine
• Catalytic MCS optimized C-models converted from MATLAB can be integrated through standard C-function calls
• Simulation output can be automatically redirected into MATLAB for analysis

   

Block Diagram Editor

• Easy graphic system capture
• Unlimited undo/redo operations
• Hierarchical block diagram environment allows easy viewing of an entire system, including system parameters and C source code
• Block terminals indicate both signal direction and connectivity status
• Acrobat-style pan mode with additional pan-overview window facilitating viewing of complex designs
• Simultaneous modification of multiple selected objects properties
• Hierarchy refactor for collapsing a group of models into one block

Library Browser

• Provides overview of libraries, models and design hierarchies with short descriptions and symbol views, logical views and structural views
• Powerful search function across entire product and user data base
• Direct link from library browser into the model documentation

Analysis

• Interactive analysis supported by predefined analysis widgets (multitrace oscilloscopes, signal generators, and spectrum analyzers, eye, scatter, x-y, parameters)
• Post-simulation analysis with rich set of plot functions and post-processing and mathematical transformations
• Very powerful C-based scripting of post-processing tasks, enabling subsequent one-click analysis
• Bit error rate (BER) and block error rate (BLER) curves are automatically merged from a large number of simulations conducted on multiple machines
• Analysis UI handles manipulation of a variety of data types, including floating-point, fixed-point and complex
• Signals and data attributes can be collated and stored in a single file for analysis
• Automatic start of MATLAB analysis from simulation results

Model Wizard

• Sophisticated infrastructure to create templates for new blocks, which may be user-written polymodels in C++, imported MATLAB functions, legacy C-functions, HDL or AMS

Workgroup/Data Management

• Control access and modifications as well as revision history and track changes option with CVS
• Extendible to other revision control infrastructures