Celoxica DK design suite提供以基于ANSI-C的Handel-C语言为基础的高阶设计方法，可在硬件中快速设计和实现复杂的运算法，除了先进的合成及时序评估工具外，DK的区域和延迟分析也可为快速最佳化提供布局前的早期时序和区域评估。该设计工具除了能输出特定FPGA平台EDIF格式外(包含Xilinx,Altera,Actel大部分的芯片)，它能输出结构化的Verilog和VHDL，并保留Handel-C原始码的层次性，因此用户能利用传统的仿真工具来除错Verilog或VHDL输出。HDL输出能用于FPGA/可程序平台，也可用于ASIC工具流程。Celoxica DK将C语言设计到FPGA的流程和方法最佳化，可让软件工程师、硬件设计者及系统架构设计师维持高性能的FPGA方案，并同时加速高可靠性、高速通讯的设计，以及从概念到实现的ASIC替代方案。

::::::English Description::::::

The DK Design Suite software is a complete ESL design environment for ANSI-C using Handel-C. It provides the benefits of system-level design using C-based design languages to FPGA and SoC. This includes system co-design and co-verification capabilities as well as C-to-RTL and direct C-to-FPGA synthesis.

Better designs, faster

• Specify, design and model systems in C
• Rapidly explore, simulate and verify diverse HW-SW architectures
• Find optimal partitions
• Synthesize directly to FPGA or RTL using the industry’s most widely used C-synthesis technology

Algorithm acceleration

• The DK Design Suite enables designers to quickly and efficiently accelerate software algorithms and system bottlenecks in parallel hardware
• Sequential C algorithms can be migrated to a parallel hardware implementation using the DK Design Suite and the necessary hardware EDIF or RTL code is automatically generated
• Coding remains at the C level throughout
  

Manage complexity and reduce risk

• Use C-based models to develop systems using layered design techniques, fast cycle-accurate simulation and mixed abstraction level modeling
• A common language and methodology for HW and SW design improves communication and reduces risk
• Maintain the testbench and share code, libraries and system models with all members of the design team from specification through to implementation

Enable the design team

• Rapid architectural exploration for system designers
• The direct implementation of complex algorithms for hardware engineers
• Fast simulation and HW-SW co-verification for verification engineers
• Easy to use design environment
• The lowest barrier entry for software engineers to accelerate their designs in hardware

DK in Action

DK provides the user with a complete flow: From specification to implementation as architecture-optimized EDIF netlist for FPGA’s and; RTL (VHDL or Verilog) used for alternative synthesis flows and other hardware targets including ASIC design.

A rapid flow from C algorithm to implementation

Rapid development with one easy-to-use tool from specification and architectural exploration through to synthesis and implementation

Optimized implementation

The best quality of design with synthesis for architecture specific features

Comprehensive simulation capability

Flexible simulation supporting mixed abstraction modeling. and verification with functional, cycle accurate simulations and third party tool connectivity

Design and IP reuse

Maximize investment with existing RTL component reuse. Deploy libraries for IP evaluation and communication between teams