Spicelink 5.0 Highlights SI 3D Distributed models (multiPEEC) w 64-bit solvers for Unix (solves w huge problems) SI 2D Loss tangents for dielectric w materials New fields postprocessor w Schematic/Spice: IBIS driver model import via w IbisLink Design Challenges Complex structures at the board, package and chip level continue to decrease in size while being expected to perform at higher speeds. As conduction paths become electrically long and approach or exceed the physical wavelength of the signal, more traditional static parasitic extraction and SPICE modeling need to be enhanced by high frequency modeling