- Size:2.8 GB
- Language:english
- Platform:Linux
- Freshtime:2010-08-10
- Search:ISE Design Suite v12.2 download crack
Description
What's New in the ISE Design Suite 12.2 for Logic Designers
Project Navigator
* SmartXplorer:
o Consistent use of TRCE options between Project Navigator and SmartXplorer.
o Ability to perform Power Analysis with SmartXplorer runs.
o Additional resource utilization data displayed in SmartXplorer Results viewer.
o Ability to customize displayed data in SmartXplorer Results viewer.
o Ability to compare multiple SmartXplorer runs.
o Ability to specify maximum number of runs to save.
* ISE® Design Summary and Report Viewer:
o Print Preview support.
o Line numbers available in Report Viewer through right-click context menu > Line Numbers.
o Index available for text-based Static Timing Report.
* ISE Text Editor:
o Wildcards supported in Find options
* RTL/Technology Viewer:
o Several bugs fixed relating to the drawing of schematics, particularly when drawing buses.
o Improvements to cross probing from Timing Analyzer to RTL/Technology Viewer.
* Schematic Editor:
o Symbol preview diagram in Symbol Wizard.
o Symbol attributes properly displayed on schematic sheet.
o Several bugs fixed relating to the drawing and netlisting of schematics.
o Mentor Graphics QuestaSim™ integrated simulation support.
Partial Reconfiguration
* What's New for Partial Reconfiguration in ISE 12.2:
o Implementation tool runtimes improved more than 20%.
o Improved DRCs.
o Support for Virtex®-6 LX/CXT low power (TL) and Qual (QX) devices.
o Support for Virtex-6 HXT devices available upon request.
o Encrypted partial bit files are supported for Virtex-6.
FPGA Editor
* List Window:
o Double-click or use the pop-up menu to zoom to selected items.
* Array Window:
o Right click to access the Hilite commands.
o Use the Select Area command to select sites and comps within a rectangular region.
* Dialog Boxes:
o New Automatic DRC on Save setting in Main Properties.
PlanAhead
* Design Preservation and Partial Reconfiguration are supported for the command line tools and the standalone version of the PlanAhead™ software.
* Spartan®-6 SSO/SSN is supported using limit tables for calculating simultaneous I/O switching output/noise.
SmartXplorer
* SmartXplorer automatically runs BITGEN for the best strategy (command line mode only).
* SmartXplorer is capable of saving only the N best results in order to efficiently manage disk space.
* Project Navigator automatically passes user-set TRCE options to SmartXplorer.
* A new check button in Project Navigator activates Power Analyzer in SmartXplorer.
* Project Navigator allows you to personalize the SmartXplorer Run Summary table.
* Area data (LUTs, Slice registers) is visible in the SmartXplorer Run Summary table.
XST
* Allows you to use the timing command to generate clock domain crossing information.