Ultimate Productivity for FPGA Logic Design The ISE® Design Suite: Logic Edition includes exclusive tools and technologies to help achieve optimal design results. These include Intelligent Clock-Gating for dynamic power reduction, Team Design for multi-site design teams, Design Preservation for timing repeatability, and Partial Reconfiguration for greater system flexibility, size, power and cost reduction. Achieve Greater Designer Productivity From product installation through design verification, ISE Design Suite 13 helps you make maximum use of your time and design resources. The ISE Design Suite - Logic Edition provides a complete design environment for your RTL-based design needs - with exclusive technologies such as ChipScope™ Pro and the ChipScope Pro Serial I/O Toolkit, ISE™ Simulator, and PlanAhead™ – along with Multi-processor support allowing distributed processing to speedup implementation. Attain Breakthrough Performance, Power and Cost Benefits ISE Design Suite: Logic Edition delivers easy to use technologies to help you achieve even the most aggressive performance goals in less time. SmartGuide, SmartXplorer, PlanAhead Design and Analysis Tool, Design Preservation. Focus on Design Differentiation The ISE Design Suite - Logic Edition is a comprehensive suite supporting the Base methodology for optimal logic and connectivity design, delivering an integrated development environment of software tools, configuration wizards, and IP that facilitates your design and utilizes all of the flexibility offered by a programmable platform. The ISE Design Suite helps remove design hurdles enabling you to more easily achieve your design goals. Xilinx CORE Generator™ System, included in all Editions of the ISE Design Suite, accelerates design time by providing access to highly parameterized Intellectual Properties (IP) and Architecture Wizards with built-in intelligent for functions like I/O and Clocking for Xilinx FPGAs. The available user-customizable IP functions range in complexity from commonly used functions, such as memories and FIFOs, to system-level building blocks, such as filters and transforms. Using these IP blocks can save days to months of design time. The highly optimized IP allows FPGA designers to focus efforts on building designs quicker while helping bring products to market faster.