Xilinx DSP TOOL 9.2.00.967包含了Xilinx System Generator 9.2和Xilinx AccelDSP 9.2

Xilinx System Generator 9.2 是业内领先的高级工具，用于借助 FPGA 来设计高性能 DSP 系统。  工具的提取功能使您能利用业内最高级的 FPGA 开发高度并行的系统，Simulink 与MATLAB（MathWorks 公司）提供了系统建模与自动代码生成。 System Generator 是 Xilinx XtremeDSP™ 解决方案的关键组成，集成了先进的 FPGA、设计工具、IP 核、合作伙伴及设计与教育培训服务等。

关键特性

• DSP 建模⁽¹⁾。利用包含信号处理（如 FIR 滤波器、FFT）、纠错（如 Viterbi 解码器、Reed-Solomon 编码器/解码器）、算法、存储器（如 FIFO、RAM、ROM）及数字逻辑功能的 Xilinx 模块集，在 Simulink 内构建和调试高性能 DSP 系统。Xilinx 模块集提供的模块可以使您导入 MATLAB 功能（如创建控制电路）及 HDL 模块（System Generator 提供到 Mentor Graphics 公司推出的 ModelSim 的 HDL 协仿真接口和 Xilinx ISE 仿真器）。
• Simulink 的 VHDL 或 Verilog 的自动代码生成。从 Xilinx 模块集实现行为（RTL）生成与对象明确的 Xilinx IP 核。同样，具有生成用 MATLAB 数写的 RTL 功能的有限（但有用）能力。 “黑盒子”HDL 模块作为大型设计的一部分提供。
• 硬件协仿真。创建“FPGA 在环路（FPGA-in-the-loop）”仿真对象是代码生成选项，允许您验证工作硬件并加速 Simulink 与 MATLAB 中的仿真。System Generator 支持以太网（10/100/千兆位）、PCI、Cardbus 及硬件平台与 Simulink 之间的 JTAG 通信。
• 嵌入式系统的硬件/软件协设计。为 Xilinx MicroBlaze™ 32 位 RISC 处理器构建和调试 DSP 协处理器。 System Generator 提供了 HW/SW 接口的共享存储器提取功能，自动生成 DSP 协处理器、总线接口逻辑、软件驱动器及协处理器使用方面的软件技术文档。

AccelDSP™ 综合工具是基于高级 MATLAB® 语言的工具，用于设计针对 Xilinx FPGA 的 DSP 块。 工具可自动地进行浮点-定点转换，生成可综合的 VHDL 或 Verilog，并创建用于验证的测试平台。您还可以生成定点 C++ 模型或由 MATLAB 算法得到 System Generator 块。AccelDSP 综合工具是 Xilinx XtremeDSP™ 解决方案的关键组成，集成了先进的 FPGA、设计工具、IP 核、合作伙伴以及设计与教育培训服务等。

关键特性

• DSP 建模 – 带有面向 Xilinx FPGA 的 MATLAB 高级 DSP 算法的设计、层次化探测与调试，可缩短设计周期，并削减设计成本。
• IP-浏览器技术 - 算法级硬件架构的启发性驱动选择生成系统优化的设计。
• 自动浮点到定点转换 – 浮点到定点转换的自动字宽选择与传送。
• 可综合 VHDL 或 Verilog 的自动代码生成 – 定点设计后生成的位精度代码可满足系统规范。
• 位精度验证 –面向自动验证的 RTL 、布局与布线后模型比较。
• C++ 仿真模型生成 - 与标准定点 MATLAB 相比，仿真速度提高了 1000 倍。
• System Generator 集成 – 生成的块可输出到大型系统内的 System Generator 中。
• 第三方集成 – 访问和集成第三方仿真与综合工具，为不熟悉 RTL 仿真与综合工具的算法设计人员简化了设计流程。

::::::English Description::::::
Xilinx DSP TOOL 9.2.00.967 include Xilinx System Generator 9.2 AND Xilinx AccelDSP 9.2.

System Generator for DSP is the industry’s leading high-level tool for designing high-performance DSP systems using FPGAs.  The tool provides abstractions that enable you to develop highly parallel systems with the industry’s most advanced FPGAs, providing system modeling and automatic code generation from Simulink® and MATLAB® (The MathWorks, Inc.).  System Generator is a key component of the Xilinx XtremeDSP™ solution that combines state-of-the-art FPGAs, design tools, intellectual property cores, and partnerships, as well as design and educational services.

Key Features

• DSP modeling⁽¹⁾. Build and debug high-performance DSP systems in Simulink using the Xilinx Blockset that contains functions for signal processing (e.g., FIR filters, FFTs), error correction (e.g., Viterbi decoder, Reed-Solomon encoder/decoder), arithmetic, memories (e.g., FIFO, RAM, ROM), and digital logic. The Xilinx Blockset also provides blocks for importing MATLAB functions (e.g., to create control circuits) and HDL modules (System Generator provides HDL co-simulation interfaces to ModelSim from Mentor Graphics and the Xilinx ISE™ Simulator).
• Automatic code generation of VHDL or Verilog from Simulink. Implement behavioral (RTL) generation and target specific Xilinx IP cores from the Xilinx Blockset. There is also a limited (but useful) ability to generate RTL for functions written in MATLAB. Deliver “black box” HDL modules as part of a larger design.
• Hardware co-simulation. Create an “FPGA-in-the-loop” simulation target: a code generation option that allows you to validate working hardware and accelerate simulations in Simulink and MATLAB. System Generator supports Ethernet (10/100/Gigabit), PCI, Cardbus, and JTAG communication between a hardware platform and Simulink.
• Hardware / software co-design of embedded systems. Build and debug DSP co-processors for the Xilinx MicroBlaze™ 32-bit RISC processor. System Generator provides a shared memory abstraction of the HW/SW interface, automatically generating the DSP co-processor, the bus interface logic, software drivers, and software documentation for using the co-processor.

AccelDSP™ Synthesis Tool is a high-level MATLAB® language based tool for designing DSP blocks for Xilinx FPGAs. The tool automates floating- to fixed-point conversion, generates synthesizable VHDL or Verilog, and creates a testbench for verification. You can also generate a fixed-point C++ model or System Generator block from a MATLAB algorithm. AccelDSP synthesis tool is a key component of the Xilinx XtremeDSP™ solution that combines state-of-the-art FPGAs, design tools, intellectual property cores, and partnerships, as well as design and educational services.

Key Features

• DSP modeling – Design, architectural exploration, and debug of high-level DSP algorithms with MATLAB for Xilinx FPGAs to reduce design cycles and costs.
• IP-Explorer Technology – Heuristic-driven selection of hardware architecture at the algorithmic level to produce system-optimized designs.
• Automated floating- to fixed-point conversion – Automated word width selection and propagation for floating- to fixed-point conversion.
• Automatic code generation of synthesizable VHDL or Verilog – Bit-accurate code generated after fixed-point design meets system specifications.
• Verification of bit-accuracy – Comparison of RTL and post-place and route model for automatic verification.
• C++ simulation model generation – Improved simulations speeds of 1000x over standard fixed-point MATLAB.
• System Generator integration – Generated blocks can be exported to System Generator for inclusion in a larger system.
• Third party integration – Access to and integration of third party simulation and synthesis tools to simplify the design flow for algorithm designers unfamiliar with RTL simulation and synthesis tools.