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Xilinx DSP TOOL 10.1i.00.967 include Xilinx System Generator 10.1i AND Xilinx AccelDSP 10.1i.

System Generator for DSP is the industry’s leading high-level tool for designing high-performance DSP systems using FPGAs.  The tool provides abstractions that enable you to develop highly parallel systems with the industry’s most advanced FPGAs, providing system modeling and automatic code generation from Simulink® and MATLAB® (The MathWorks, Inc.).  System Generator is a key component of the Xilinx XtremeDSP™ solution that combines state-of-the-art FPGAs, design tools, intellectual property cores, and partnerships, as well as design and educational services.

Key Features

• DSP modeling⁽¹⁾. Build and debug high-performance DSP systems in Simulink using the Xilinx Blockset that contains functions for signal processing (e.g., FIR filters, FFTs), error correction (e.g., Viterbi decoder, Reed-Solomon encoder/decoder), arithmetic, memories (e.g., FIFO, RAM, ROM), and digital logic. The Xilinx Blockset also provides blocks for importing MATLAB functions (e.g., to create control circuits) and HDL modules (System Generator provides HDL co-simulation interfaces to ModelSim from Mentor Graphics and the Xilinx ISE™ Simulator).
• Automatic code generation of VHDL or Verilog from Simulink. Implement behavioral (RTL) generation and target specific Xilinx IP cores from the Xilinx Blockset. There is also a limited (but useful) ability to generate RTL for functions written in MATLAB. Deliver “black box” HDL modules as part of a larger design.
• Hardware co-simulation. Create an “FPGA-in-the-loop” simulation target: a code generation option that allows you to validate working hardware and accelerate simulations in Simulink and MATLAB. System Generator supports Ethernet (10/100/Gigabit), PCI, Cardbus, and JTAG communication between a hardware platform and Simulink.
• Hardware / software co-design of embedded systems. Build and debug DSP co-processors for the Xilinx MicroBlaze™ 32-bit RISC processor. System Generator provides a shared memory abstraction of the HW/SW interface, automatically generating the DSP co-processor, the bus interface logic, software drivers, and software documentation for using the co-processor.

AccelDSP™ Synthesis Tool is a high-level MATLAB® language based tool for designing DSP blocks for Xilinx FPGAs. The tool automates floating- to fixed-point conversion, generates synthesizable VHDL or Verilog, and creates a testbench for verification. You can also generate a fixed-point C++ model or System Generator block from a MATLAB algorithm. AccelDSP synthesis tool is a key component of the Xilinx XtremeDSP™ solution that combines state-of-the-art FPGAs, design tools, intellectual property cores, and partnerships, as well as design and educational services.

Key Features

• DSP modeling – Design, architectural exploration, and debug of high-level DSP algorithms with MATLAB for Xilinx FPGAs to reduce design cycles and costs.
• IP-Explorer Technology – Heuristic-driven selection of hardware architecture at the algorithmic level to produce system-optimized designs.
• Automated floating- to fixed-point conversion – Automated word width selection and propagation for floating- to fixed-point conversion.
• Automatic code generation of synthesizable VHDL or Verilog – Bit-accurate code generated after fixed-point design meets system specifications.
• Verification of bit-accuracy – Comparison of RTL and post-place and route model for automatic verification.
• C++ simulation model generation – Improved simulations speeds of 1000x over standard fixed-point MATLAB.
• System Generator integration – Generated blocks can be exported to System Generator for inclusion in a larger system.
• Third party integration – Access to and integration of third party simulation and synthesis tools to simplify the design flow for algorithm designers unfamiliar with RTL simulation and synthesis tools.