Overview IC Compiler is an integral part of the Synopsys Galaxy™ Implementation Platform that delivers a comprehensive design solution, including synthesis, physical implementation, low-power design, and design for manufacturability. IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, manufacturability, and low-power capabilities that enable designers to implement today’s high-performance, complex designs on schedule. Download Datasheet IC Compiler is a comprehensive place-and-route system; it provides best QoR in timing, area, power, signal integrity, routability, out-of the-box results and faster design closure. Multicore support throughout the flow delivers improved productivity. New technologies enable designers to handle gigascale, complex designs and meet tight project schedules. IC Compiler is tightly correlated to the industry-standard signoff solutions – PrimeTime® SI and StarRC™. Additionally, it provides an optimal physical ECO implementation solution with PrimeTime ECO Guidance. Growing design complexity, ever-increasing DRC rules and complex manufacturing compliance needs have rendered the prevailing implement-thenverify approach to physical verification suboptimal. In-Design technology made possible by the seamless integration of IC Validator DRC/LVS signoff solution and IC Compiler, allows designers to mitigate these challenges in the implementation stage for faster signoff closure. IC Compiler provides a comprehensive manufacturability solution that concurrently optimizes for yield with timing, area, power, test, and routability. IC Compiler increases manufacturability of the design, optimizing both functional and parametric yield. IC Compiler with concurrent hierarchical design enables powerful design planning and chiplevel feasibility, analysis features to handle large, complex designs. Providing early analysis and feasibility exploration, IC Compiler delivers smaller die size and achieves predictable design closure to reduce the cost of design. IC Compiler with Zroute technology utilizes advanced routing algorithms, concurrent manufacturability optimizations and multi-threading, to improve manufacturability and deliver much faster turn-around-time. IC Compiler with strong links to Design Compiler® Graphical, PrimeTime-SI, StarRC, IC Validator and PrimeRail faster design convergence and strong productivity benefits to all designers. Figure 1: Synopsys Galaxy Implementation Platform Benefits QoR Innovative technology in IC Compiler delivers improved QoR, measured in terms of the complete cost vector – timing, area, power, signal integrity, routability, and manufacturability. Concurrent multicorner multimode (MCMM) optimization across the flow, enhanced signal integrity capabilities, Multisource Clock Tree Synthesis (MSCTS) and physical datapath technology enable designers to meet aggressive QoR targets for gigascale, complex chips and high-performance cores at advanced technology nodes. “Physical Datapath” technology allows designers to create structures by specifying constraints for the relative column and row positions of instances. These structures are called relative placement (RP) structures. Figure 2 highlights some of the benefits of relative placement (RP).