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Synopsys?JupiterXT™ design planning solution enables fast feasibility analysis for a preview of implementation results, and provides detailed floor planning capabilities for flat or hierarchical physical design implementation styles.

Project leaders and physical designers of ASIC or COT designs benefit from the accurate prediction and production-proven convergence JupiterXT provides.

Feasibility analysis is supported for incomplete netlists in the form of black boxes or early gate level netlists. Powerful placement algorithms incorporate designers?knowledge of black box content and produce routable floorplan results using autoshaping with full rectilinear support. If gate netlists are available, the placement algorithms apply a virtual flat approach that places hard macros and standard cells simultaneously.

As more detailed design content is added to netlists as a result of module synthesis, the feasibility results are re-used to guide detailed floorplanning. The core placement, routing extraction and delay calculation engines are common to Synopsys?detailed implementation tool, IC Compiler, ensuring the fastest convergence to routable, timing correct floorplans. Design and library data is read and written from Synopsys?Milkyway™ database enabling efficient transfers into and from the design planning task.

Key Benefits

• Fast and accurate feasibility studies
• Best prediction of IC Compiler results
• Increased productivity through automation
• Runtime and capacity to address the largest of your designs
• Supports multiple implementation styles

Figure 1: Input and Output from JupiterXT

Figure 2: Stages of Design Planning

Design Challenges
As new process nodes are introduced, larger and larger designs are possible. With increasing design sizes, more complex SoC systems are being designed. To handle the large number of gates in a design, designers are using more hard macros. Clock speeds on designs are on the rise-some operating in the GHz range. Leakage currents of devices at smaller process nodes are also increasing. These are just some of the technical factors contributing to the increased complexity of today抯 SoC design starts. Additionally, market pressures are unrelenting and the time available for design teams to get from RTL to GDSII is shrinking. Design teams are faced with implementing larger, more complex designs, while dealing with placement, routing, timing, and power closure, in shorter periods of time. The challenges addressed by JupiterXT design planning are:

• The need to assess the feasibility of larger, faster, more power hungry designs
• The need to finalize design floorplans in shorter amounts of time in the smallest possible sizes.

Physical Prototyping And Detailed Floorplanning
It is general practice to start physical implementation of designs early, before the completion of logic design. Physical design teams must accept very early versions of the design netlist and start work on physical prototyping. During this period, physical designers are expected to determine if the design can be implemented in the required area, if the design can operate at the desired speed, and if the design can meet power requirements. To meet area requirements, the design must be routable. To operate at the desired speed, the design must meet timing requirements. To meet power requirements, the power structures must deliver power to the core within acceptable voltage drop and electromigration limits. It is imperative that physical designers are afforded the opportunity to explore as much of the physical solution space as possible in this time to enable the most informed assessment of feasibility.

JupiterXT provides fast, automatic placement, power network synthesis, global routing, and in-place optimization to enable designers to quickly generate prototype floorplans. JupiterXT provides a complete set of integrated analysis capabilities to enable designers to assess routability, timing, and power correctness. Near the end of the design planning process the changes to the floorplan become smaller. The objective switches to producing the best optimized floorplan to quickly close the design. This stage is referred to as detailed floorplaning. Powerful editing capabilities coupled with the integrated analysis tools enable designers to quickly ?and accurately ?perform final floorplan changes that may be needed to squeeze the last parsec of performance out of the design.

Best Prediction Of IC Compiler Results
A key component for successful completion of design planning is accurate prediction. If the predicted results are not correlated to the results from the detailed implementation tools, then they are of little value.

JupiterXT uses the same core engines for placement, routing, extraction, delay calculation and in-place optimization, as Synopsys?IC Compiler. Power Network Analysis is correlated to sign-off proven PowerRail. Regression suites containing many customer designs are run during every release cycle to ensure design planning results continue to track signoff. What you see in JupiterXT is the best prediction of actual detailed implementation results.

Increased Productivity
Included with each release of JupiterXT is a suite of Recommended Methodology (JRM) scripts. The scripts ease adoption by automating the physical prototyping phase of design planning. Simply set-up pointers to library and netlist data, then run. For the physical prototyping, the JRM scripts generate multiple floorplans and present results in a simple html table. Embedded in the table are links to enable one-click access to analysis reports and plots. Following the JRM flow enables generation of multiple floorplans for large designs overnight. Explore the maximum number of solutions during the physical prototyping phase. Designer time is freed up and focused on analysis of results, therefore maximizing productivity.

Runtime And Capacity To Address The Largest Of Your Designs
Recent trends show fewer design starts, but the average design size (in terms of gates) is dramatically increasing. Multi-million gate designs are becoming the norm. And this trend is continuing.

The JupiterXT development team is constantly working on ways to improve runtime and capacity. And it抯 paying off. At San Jose SNUG, one of our customers presented a paper on how they used JupiterXT on a recent, 40 Million plus gate design. With the virtual flat capabilities of JupiterXT, they could place, global route, and time the complete design overnight!

Supports Multiple Implementation Styles
Flat or hierarchical, single or multi-Vdd, JupiterXT supports them all. The fast placement, power network synthesis, global routing, and in-place optimization capabilities ?all based on production proven core implementation engines ?provide the infrastructure for any methodology.

Hierarchical designs need more. Physical designers need to assess how best to partition the logical hierarchy into physical modules. Then, they must be able to generate complete timing and physical constraints for each of the physical modules. JupiterXT provides powerful hierarchy manipulation and visualization capabilities to enable creation of the best physical partitions. And the hierarchy management includes SDC management. Trace-mode timing enables fast and focused analysis of top-level timing without requiring the creation of timing models for the physical partitions. Top-level clock planning capabilities enable accurate prediction of clock distribution networks that span multiple physical partitions. Pin assignment and physical push-up/push-down capabilities enable quick generation of physical constraints. The time budgeter enables generation of timing constraints ?considering predicted clock latencies - for each partition.

Multi-VDD designs need more. Physical designers must divide the physical placement area of the chip up into voltage areas. Given voltage areas, designers must deal with the placement needs of level shifters between areas. And of course, the power network creation and timing optimization tasks are further complicated. Another type of a multi-VDD design is an MTCMOS design. In this style, in addition to creating voltage areas, designers must add switch cells (headers or footers) to enable isolation of VDD/VSS leakage current paths. In the physical prototyping phase, JupiterXT placement can be used as a guide for locating, sizing, and shaping of voltage areas. MTCMOS voltage areas can be isolated with switch cells. During the detailed floorplanning phase, the placement is voltage area aware. It also recognizes level shifters and ensures their placement close to voltage area interfaces, if required. The Power Network Synthesis capability can be applied to designs with multiple voltage areas. In-place optimization is voltage area aware. JupiterXT provides a comprehensive solution for todays design challenges. For flat or hierarchical design styles, for prototyping or detailed floorplanning JupiterXT delivers the fastest path to routable floorplans. JupiterXT is the recommended design planner of the Galaxy Physical Design Solution.